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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
CalcSpillWeights.h 48 LiveIntervals &LIS;
58 VirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS,
61 : MF(MF), LIS(LIS), VRM(VRM), Loops(Loops), MBFI(MBFI) {}
LiveRegMatrix.h 42 LiveIntervals *LIS;
LiveRangeEdit.h 74 LiveIntervals &LIS;
133 /// @param lis The collection of all live intervals in this function.
140 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm,
143 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
237 /// to erase it from LIS.
ModuloSchedule.h 173 LiveIntervals &LIS;
262 LiveIntervals &LIS, InstrChangesTy InstrChanges)
264 TII(ST.getInstrInfo()), LIS(LIS),
282 LiveIntervals *LIS)
284 TII(ST.getInstrInfo()), LIS(LIS) {}
298 LiveIntervals *LIS;
RegAllocPBQP.h 140 LiveIntervals &LIS,
142 : MF(MF), LIS(LIS), MBFI(MBFI) {}
145 LiveIntervals &LIS;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocBase.h 67 LiveIntervals *LIS = nullptr;
81 void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
InterferenceCache.h 62 /// LIS - Used for accessing register mask interference maps.
63 LiveIntervals *LIS = nullptr;
103 void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
108 LIS = lis;
168 SlotIndexes *indexes, LiveIntervals *lis,
RenameIndependentSubregs.cpp 72 SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR,
74 : ConEQ(LIS), SR(&SR), Index(Index) {}
104 LiveIntervals *LIS;
143 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
162 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents));
189 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
223 SlotIndex Pos = LIS->getInstructionIndex(*MI);
271 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
303 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
304 const SlotIndexes &Indexes = *LIS->getSlotIndexes()
    [all...]
SplitKit.h 53 const LiveIntervals &LIS;
65 InsertPointAnalysis(const LiveIntervals &lis, unsigned BBNum);
84 SlotIndex Res = LIS.getMBBStartIdx(&MBB);
88 Res = LIS.getInstructionIndex(*MII);
101 const LiveIntervals &LIS;
173 SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
269 LiveIntervals &LIS;
462 SplitEditor(SplitAnalysis &SA, AAResults &AA, LiveIntervals &LIS,
PHIElimination.cpp 70 LiveIntervals *LIS;
151 LIS = getAnalysisIfAvailable<LiveIntervals>();
156 if (!DisableEdgeSplitting && (LV || LIS)) {
205 if (LIS)
206 LIS->RemoveMachineInstrFromMaps(*DefMI);
213 if (LIS)
214 LIS->RemoveMachineInstrFromMaps(*I.first);
379 if (LIS) {
380 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(*PHICopy);
382 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB)
    [all...]
VirtRegMap.cpp 182 LiveIntervals *LIS;
250 LIS = &getAnalysis<LiveIntervals>();
257 LIS->addKillFlags(VRM);
329 LiveInterval &LI = LIS->getInterval(VirtReg);
330 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
373 const LiveInterval &LI = LIS->getInterval(Reg);
375 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
498 SlotIndex MIIndex = LIS->getInstructionIndex(MI);
502 const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
623 if (LIS) {
    [all...]
RegAllocPBQP.cpp 162 void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
169 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
181 void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
184 void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
193 LiveIntervals &LIS = G.getMetadata().LIS;
201 LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight();
310 LiveIntervals &LIS = G.getMetadata().LIS;
334 LiveInterval &LI = LIS.getInterval(VReg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyOptimizeLiveIntervals.cpp 75 auto &LIS = getAnalysis<LiveIntervals>();
91 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
112 LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
113 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
114 LIS.RemoveMachineInstrFromMaps(*MI);
WebAssemblyMemIntrinsicResults.cpp 88 LiveIntervals &LIS) {
91 LiveInterval *FromLI = &LIS.getInterval(FromReg);
92 LiveInterval *ToLI = &LIS.getInterval(ToReg);
94 SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot();
109 SlotIndex WhereIdx = LIS.getInstructionIndex(*Where);
134 LIS.extendToIndices(*ToLI, Indices);
137 LIS.shrinkToUses(FromLI);
151 MachineDominatorTree &MDT, LiveIntervals &LIS,
174 return replaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS);
189 auto &LIS = getAnalysis<LiveIntervals>()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCTLSDynamicCall.cpp 46 LiveIntervals *LIS;
189 LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
207 LIS = &getAnalysis<LiveIntervals>();
PPCVSXFMAMutate.cpp 67 LiveIntervals *LIS;
109 SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
118 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill()
213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
281 LiveInterval &FMAInt = LIS->getInterval(OldFMAReg);
299 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
308 LIS->getVNInfoAllocator())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPreAllocateWWMRegs.cpp 35 LiveIntervals *LIS;
101 LiveInterval &LI = LIS->getInterval(Reg);
148 LIS->removeInterval(Reg);
207 LIS = &getAnalysis<LiveIntervals>();
GCNIterativeScheduler.cpp 47 const LiveIntervals *LIS,
56 if (!I->isDebugInstr() && LIS)
57 OS << LIS->getInstructionIndex(*I);
63 if (!I->isDebugInstr() && LIS)
64 OS << LIS->getInstructionIndex(*I);
69 if (LIS) OS << LIS->getInstructionIndex(*End) << '\t';
78 const LiveIntervals *LIS) {
82 const auto LiveIns = getLiveRegsBefore(*Begin, *LIS);
87 const auto LiveOuts = getLiveRegsAfter(*BottomMI, *LIS);
    [all...]
GCNNSAReassign.cpp 75 LiveIntervals *LIS;
214 if (!LIS->hasInterval(Reg))
236 LIS = &getAnalysis<LiveIntervals>();
284 LiveInterval *LI = &LIS->getInterval(Reg);
296 MinInd = MaxInd = LIS->getInstructionIndex(*MI);
322 return LIS->getInstructionIndex(*C.first) < I;
325 LIS->getInstructionIndex(*I->first) < MaxInd; ++I) {
GCNRegPressure.h 112 const LiveIntervals &LIS;
118 GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
150 // filling live regs upon this point using LIS
157 // to reported by LIS
173 // filling live regs upon this point using LIS.
198 const LiveIntervals &LIS,
202 const LiveIntervals &LIS,
212 getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
215 auto &SII = *LIS.getSlotIndexes();
227 if (!LIS.hasInterval(Reg)
    [all...]
SIFormMemoryClauses.cpp 271 LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
272 SlotIndexes *Ind = LIS->getSlotIndexes();
281 GCNDownwardRPTracker RPT(*LIS);
338 SlotIndex ClauseLiveInIdx = LIS->getInstructionIndex(MI);
340 LIS->getInstructionIndex(*LastClauseInst).getNextIndex();
354 const LiveInterval &LI = LIS->getInterval(R.first);
409 LIS->removeInterval(Reg);
410 LIS->createAndComputeVirtRegInterval(Reg);
417 LIS->removeInterval(Reg);
418 LIS->createAndComputeVirtRegInterval(Reg)
    [all...]
SILowerSGPRSpills.cpp 45 LiveIntervals *LIS = nullptr;
83 LiveIntervals *LIS) {
109 if (LIS) {
113 LIS->InsertMachineInstrInMaps(Inst);
114 LIS->removeAllRegUnitsForPhysReg(Reg);
123 LiveIntervals *LIS) {
146 if (LIS) {
148 LIS->InsertMachineInstrInMaps(Inst);
149 LIS->removeAllRegUnitsForPhysReg(Reg);
233 insertCSRSaves(*SaveBlock, CSI, LIS);
    [all...]
SIOptimizeExecMaskingPreRA.cpp 33 LiveIntervals *LIS;
91 LiveIntervals *LIS, Register Reg,
93 SlotIndex AndIdx = LIS->getInstructionIndex(And);
94 SlotIndex SelIdx = LIS->getInstructionIndex(Sel);
97 return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx);
100 if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx))
133 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS);
149 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);
163 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS);
182 if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And)
    [all...]
SILowerControlFlow.cpp 71 LiveIntervals *LIS = nullptr;
264 if (!LIS) {
269 LIS->InsertMachineInstrInMaps(*CopyExec);
273 LIS->ReplaceMachineInstrInMaps(MI, *And);
276 LIS->InsertMachineInstrInMaps(*Xor);
277 LIS->InsertMachineInstrInMaps(*SetExec);
278 LIS->InsertMachineInstrInMaps(*NewBr);
280 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
286 LIS->removeInterval(SaveExecReg);
287 LIS->createAndComputeVirtRegInterval(SaveExecReg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TileConfig.cpp 84 LiveIntervals &LIS = getAnalysis<LiveIntervals>();
171 LIS.InsertMachineInstrInMaps(*NewMI);
186 SlotIndex SIdx = LIS.InsertMachineInstrInMaps(*NewMI);
187 LIS.extendToIndices(LIS.getInterval(R), {SIdx.getRegSlot()});

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