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    Searched defs:LOAD (Results 1 - 25 of 47) sorted by relevancy

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  /src/common/dist/zlib/
infback.c 121 /* Load returned state from inflate_fast() */
122 #define LOAD() \
478 LOAD();
inflate.c 445 /* Load registers with state in inflate() for speed */
446 #define LOAD() \
538 input left to load n bits into the accumulator, or it continues. BITS(n)
625 LOAD();
1039 LOAD();
  /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_generichash/blake2b/ref/
blake2b-compress-avx2.h 11 #define LOAD(p) _mm256_load_si256((__m256i *) (p))
81 #include "blake2b-load-avx2.h"
130 __m256i c = LOAD(&blake2b_IV[0]); \
132 XOR(LOAD(&blake2b_IV[4]), _mm256_set_epi64x(f1, f0, t1, t0)); \
  /src/external/gpl3/binutils/dist/zlib/
infback.c 119 /* Load returned state from inflate_fast() */
120 #define LOAD() \
476 LOAD();
inflate.c 443 /* Load registers with state in inflate() for speed */
444 #define LOAD() \
536 input left to load n bits into the accumulator, or it continues. BITS(n)
616 LOAD();
1030 LOAD();
  /src/external/gpl3/binutils.old/dist/zlib/
infback.c 127 /* Load returned state from inflate_fast() */
128 #define LOAD() \
489 LOAD();
inflate.c 476 /* Load registers with state in inflate() for speed */
477 #define LOAD() \
569 input left to load n bits into the accumulator, or it continues. BITS(n)
652 LOAD();
1065 LOAD();
  /src/external/gpl3/gdb/dist/zlib/
infback.c 127 /* Load returned state from inflate_fast() */
128 #define LOAD() \
489 LOAD();
inflate.c 476 /* Load registers with state in inflate() for speed */
477 #define LOAD() \
569 input left to load n bits into the accumulator, or it continues. BITS(n)
652 LOAD();
1065 LOAD();
  /src/external/gpl3/gdb.old/dist/zlib/
infback.c 127 /* Load returned state from inflate_fast() */
128 #define LOAD() \
489 LOAD();
inflate.c 476 /* Load registers with state in inflate() for speed */
477 #define LOAD() \
569 input left to load n bits into the accumulator, or it continues. BITS(n)
652 LOAD();
1065 LOAD();
  /src/crypto/external/apache2/openssl/dist/crypto/
mem.c 31 #define LOAD(x) 0
38 #define LOAD(x) tsan_load(&x)
91 *mcount = LOAD(malloc_count);
93 *rcount = LOAD(realloc_count);
95 *fcount = LOAD(free_count);
  /src/crypto/external/bsd/openssl/dist/crypto/
mem.c 31 # define LOAD(x) 0
38 # define LOAD(x) tsan_load(&x)
88 *mcount = LOAD(malloc_count);
90 *rcount = LOAD(realloc_count);
92 *fcount = LOAD(free_count);
  /src/external/bsd/libevent/dist/
evthread_win32.c 117 #define LOAD(name) \
119 LOAD(InitializeConditionVariable);
120 LOAD(SleepConditionVariableCS);
121 LOAD(WakeAllConditionVariable);
122 LOAD(WakeConditionVariable);
  /src/external/bsd/ntp/dist/sntp/libevent/
evthread_win32.c 116 #define LOAD(name) \
118 LOAD(InitializeConditionVariable);
119 LOAD(SleepConditionVariableCS);
120 LOAD(WakeAllConditionVariable);
121 LOAD(WakeConditionVariable);
  /src/external/cddl/osnet/dist/uts/common/zmod/
inflate.c 409 /* Load registers with state in inflate() for speed */
410 #define LOAD() \
507 input left to load n bits into the accumulator, or it continues. BITS(n)
590 LOAD();
975 LOAD();
  /src/external/gpl3/binutils/dist/opcodes/
arc-tbl.h 9014 { "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9017 { "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9020 { "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9023 { "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9026 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9029 { "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9032 { "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
9035 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9038 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9041 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
arc-tbl.h 9014 { "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9017 { "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9020 { "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9023 { "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9026 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9029 { "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9032 { "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
9035 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9038 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9041 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
arc-tbl.h 9014 { "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9017 { "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9020 { "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9023 { "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9026 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9029 { "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9032 { "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
9035 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9038 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9041 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
arc-tbl.h 9014 { "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9017 { "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9020 { "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9023 { "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9026 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9029 { "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }},
9032 { "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }},
9035 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9038 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }},
9041 { "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}
    [all...]
  /src/usr.bin/xlint/lint1/
op.h 120 LOAD,
  /src/lib/libcrypt/
crypt.c 74 * define "MUST_ALIGN" if your compiler cannot load/store
257 #define LOAD(d,d0,d1,bl) d0 = (bl).b32.i0, d1 = (bl).b32.i1
268 LOAD(d,d0,d1,(p)[(0<<CHUNKBITS)+(cpp)[0]]); \
277 LOAD(d,d0,d1,(p)[(0<<CHUNKBITS)+(cpp)[0]]); \
286 { C_block tblk; permute(cpp,&tblk,p,8); LOAD (d,d0,d1,tblk); }
288 { C_block tblk; permute(cpp,&tblk,p,4); LOAD (d,d0,d1,tblk); }
765 LOAD(L,L0,L1,B);
767 LOAD(L,L0,L1,*(const C_block *)in);
  /src/sys/dev/scsipi/
scsi_tape.h 97 #define LOAD 0x1b
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMemoryLegalizer.cpp 43 LOAD = 1u << 0,
240 /// \returns Load info if \p MI is a load operation, "None" otherwise.
285 /// Update \p MI memory load instruction to bypass any caches up to
511 /// Expands load operation \p MI. Returns true if instructions are
847 // Only handle load and store, not atomic read-modify-write insructions. The
852 // Only update load and store, not LLVM IR atomic read-modify-write
856 assert( Op == SIMemOp::LOAD || Op == SIMemOp::STORE);
861 if (Op == SIMemOp::LOAD)
876 // Request L1 MISS_EVICT and L2 STREAM for load and store instructions
    [all...]
  /src/tests/lib/libc/sys/
t_futex_ops.c 54 #define LOAD(x) (*(volatile int *)(x))
303 } while (LOAD(d->futex_ptr) != 0);
311 } while (LOAD(d->futex_ptr) != 3);
365 if (LOAD(futex_ptr) == 1)
370 ATF_REQUIRE_EQ_MSG((n = LOAD(futex_ptr)), 1, "LOAD(futex_ptr)=%d", n);
377 LOAD(error_ptr)));
380 if (LOAD(error_ptr) == -1)
385 ATF_REQUIRE_EQ_MSG((n = LOAD(error_ptr)), -1, "error=%d", n);
397 LOAD(error_ptr)))
    [all...]

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