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    Searched defs:Lanes (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonShuffler.cpp 115 unsigned Lanes;
116 const unsigned Units = HexagonConvertUnits(ItinUnits, &Lanes);
118 if (Units == 0 && Lanes == 0) {
129 setLanes(Lanes);
137 unsigned Lanes;
141 static unsigned makeAllBits(unsigned startBit, unsigned Lanes)
143 for (unsigned i = 1; i < Lanes; ++i)
156 unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes);
336 inst.Lanes = I->CVI.getLanes();
HexagonShuffler.h 86 unsigned Lanes;
92 void setLanes(unsigned l) { Lanes = l; }
102 unsigned getLanes() const { return Lanes; }
  /src/external/apache2/llvm/dist/clang/utils/TableGen/
MveEmitter.cpp 122 // same number of lanes as the input vector type. So our Predicate type
290 unsigned Lanes;
293 VectorType(const ScalarType *Element, unsigned Lanes)
294 : CRegularNamedType(TypeKind::Vector), Element(Element), Lanes(Lanes) {}
295 unsigned sizeInBits() const override { return Lanes * Element->sizeInBits(); }
296 unsigned lanes() const { return Lanes; } function in class:__anon3610::VectorType
300 return Element->cNameBase() + "x" + utostr(Lanes);
304 utostr(Lanes) + ")"
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  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ConstantFolding.cpp 2903 unsigned Lanes = FVTy->getNumElements();
2906 // sure we get the limit right in that case and set all relevant lanes.
2911 for (unsigned i = 0; i < Lanes; i++) {
2925 unsigned Lanes = FVTy->getNumElements();
2930 for (unsigned i = 0; i < Lanes; i++) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.h 464 SmallVector<MCPhysReg, 32> Lanes;
544 : I->second.Lanes[Lane];
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 752 int Lanes = 1;
754 Lanes = SrcTy.getVectorNumElements();
757 return Lanes;
759 return Lanes * CallCost;
1976 // tail-predication masks/predicates the right lanes.
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 1679 const size_t Lanes = Op.getNumOperands();
1683 // possible number of lanes at once followed by a sequence of replace_lane
1684 // instructions to individually initialize any remaining lanes.
1687 // swizzled lanes should be given greater weight.
1690 // lanes to fill gaps.
1722 // that vector. The source vector must not have more lanes than the dest
1723 // because the shufflevector indices are in terms of the destination lanes and
1724 // would not be able to address the smaller individual source lanes.
1765 // Count eligible lanes for each type of vector creation op
1766 for (size_t I = 0; I < Lanes; ++I)
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegisterCoalescer.cpp 251 /// LaneMask are split as necessary. @p LaneMask are the lanes that
302 /// If the given machine operand reads only undefined lanes add an undef
980 // Even if we are dealing with a full copy, some lanes can
1006 // IntA has undef lanes that are defined in IntB.
1485 // lanes. Assign that lane a dead def so that the interferences
1780 // The unused lanes are just empty live-ranges at this point.
1783 // unused lanes. This may happen with rematerialization.
1863 // A def of a subregister may be a use of other register lanes. Replacing
1930 // Track incoming undef lanes we need to eliminate from the subrange.
1953 LLVM_DEBUG(dbgs() << "Pruning undef incoming lanes:
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