| /src/external/apache2/llvm/dist/clang/lib/Index/ |
| FileIndexRecord.cpp | 49 const MacroInfo *MI) {
50 addOccurrence(Decls, DeclOccurrence(Roles, Offset, Name, MI));
56 if (const auto *MI = D.DeclOrMacro.dyn_cast<const MacroInfo *>())
57 return MI->isUsedForHeaderGuard();
76 const auto *MI = DclInfo.DeclOrMacro.get<const MacroInfo *>();
77 SourceLocation Loc = SM.getFileLoc(MI->getDefinitionLoc());
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 26 MachineInstr *MI = MIB;
27 MachineFunction &MF = *MI->getParent()->getParent();
29 const MCInstrDesc &MCID = MI->getDesc();
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/ |
| UniqueVector.h | 59 typename std::map<T, unsigned>::const_iterator MI = Map.find(Entry);
62 if (MI != Map.end()) return MI->second;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| DeadMachineInstructionElim.cpp | 26 #define DEBUG_TYPE "dead-mi-elimination"
51 bool isDead(const MachineInstr *MI) const;
62 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
66 if (MI->isInlineAsm())
70 if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
75 if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI())
79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80 const MachineOperand &MO = MI->getOperand(i);
98 if (&Use != MI)
[all...] |
| FinalizeISel.cpp | 57 MachineInstr &MI = *MBBI++;
59 // If MI is a pseudo, expand it.
60 if (MI.usesCustomInsertionHook()) {
62 MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
|
| RegAllocBase.cpp | 117 MachineInstr *MI = nullptr;
122 MI = &*(I++);
123 if (MI->isInlineAsm())
131 else if (MI && MI->isInlineAsm()) {
132 MI->emitError("inline assembly requires more registers than available");
133 } else if (MI) {
135 MI->getParent()->getParent()->getMMI().getModule()->getContext();
|
| TargetRegisterInfo.cpp | 72 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
73 if (MI && TII->isTriviallyReMaterializable(*MI) &&
598 const MachineInstr *MI = MRI->getVRegDef(SrcReg);
599 if (!MI->isCopyLike())
603 if (MI->isCopy())
604 CopySrcReg = MI->getOperand(1).getReg();
606 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
607 CopySrcReg = MI->getOperand(2).getReg();
620 const MachineInstr *MI = MRI->getVRegDef(SrcReg)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFRegisterInfo.cpp | 62 MachineInstr &MI = *II;
63 MachineBasicBlock &MBB = *MI.getParent();
65 DebugLoc DL = MI.getDebugLoc();
75 while (!MI.getOperand(i).isFI()) {
77 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
81 int FrameIndex = MI.getOperand(i).getIndex();
84 if (MI.getOpcode() == BPF::MOV_rr) {
88 MI.getOperand(i).ChangeToRegister(FrameReg, false);
89 Register reg = MI.getOperand(i - 1).getReg();
97 MI.getOperand(i + 1).getImm()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonHazardRecognizer.cpp | 40 MachineInstr *MI = SU->getInstr();
41 if (!MI || TII->isZeroCost(MI->getOpcode()))
44 if (!Resources->canReserveResources(*MI)) {
45 LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
47 if (TII->mayBeNewStore(*MI)) {
50 MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
55 MachineFunction *MF = MI->getParent()->getParent();
57 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCShuffler.cpp | 38 MCInst &MI = *const_cast<MCInst *>(I.getInst());
39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode())
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo());
43 if (!HexagonMCInstrInfo::isImmext(MI)) {
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI));
47 Extender = &MI;
64 MCInst &MI = *const_cast<MCInst *>(I.getInst());
65 if (!HexagonMCInstrInfo::isImmext(MI)) {
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kInstrBuilder.h | 60 MachineInstr *MI = MIB;
61 MachineFunction &MF = *MI->getParent()->getParent();
63 const MCInstrDesc &MCID = MI->getDesc();
77 MachineInstr *MI = MIB;
78 MachineFunction &MF = *MI->getParent()->getParent();
80 const MCInstrDesc &MCID = MI->getDesc();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 36 MachineInstr *MI = &MBB.front();
55 MI = BuildMI(MBB, MI, dl,
60 BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
|
| NVPTXRegisterInfo.cpp | 117 MachineInstr &MI = *II;
118 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
120 MachineFunction &MF = *MI.getParent()->getParent();
122 MI.getOperand(FIOperandNum + 1).getImm();
125 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
126 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCEarlyReturn.cpp | 80 MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
81 (*PI)->insert(J, MI);
93 MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
94 MI->setDesc(TII->get(PPC::BCCLR));
95 MachineInstrBuilder(*ReturnMBB.getParent(), MI)
98 (*PI)->insert(J, MI);
110 MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
111 MI->setDesc(
113 MachineInstrBuilder(*ReturnMBB.getParent(), MI)
115 (*PI)->insert(J, MI);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVCleanupVSETVLI.cpp | 55 static bool isRedundantVSETVLI(MachineInstr &MI, MachineInstr *PrevVSETVLI) {
58 if (!PrevVSETVLI || !MI.getOperand(0).isDead())
63 int64_t VTYPEImm = MI.getOperand(2).getImm();
67 if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
73 return PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm();
76 assert(MI.getOpcode() == RISCV::PseudoVSETVLI);
77 Register AVLReg = MI.getOperand(1).getReg();
81 if (AVLReg == RISCV::X0 && MI.getOperand(0).getReg() == RISCV::X0)
117 MachineInstr &MI = *MII++;
119 if (MI.getOpcode() != RISCV::PseudoVSETVLI &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| LeonPasses.cpp | 48 MachineInstr &MI = *MBBI;
49 unsigned Opcode = MI.getOpcode();
83 MachineInstr &MI = *MBBI;
84 unsigned Opcode = MI.getOpcode();
85 if (Opcode == SP::CALL && MI.getNumOperands() > 0) {
86 MachineOperand &MO = MI.getOperand(0);
135 MachineInstr &MI = *MBBI;
136 unsigned Opcode = MI.getOpcode();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyLowerBrUnless.cpp | 67 MachineInstr *MI = &*MII++;
68 if (MI->getOpcode() != WebAssembly::BR_UNLESS)
71 Register Cond = MI->getOperand(1).getReg();
192 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
202 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
203 .add(MI->getOperand(0))
205 MBB.erase(MI);
|
| WebAssemblyOptimizeLiveIntervals.cpp | 110 MachineInstr *MI = &*MII++;
111 if (MI->isImplicitDef() && MI->getOperand(0).isDead()) {
112 LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
113 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
114 LIS.RemoveMachineInstrFromMaps(*MI);
115 MI->eraseFromParent();
|
| WebAssemblyPrepareForLiveIntervals.cpp | 116 MachineInstr &MI = *MII++;
117 if (WebAssembly::isArgument(MI.getOpcode())) {
118 MI.removeFromParent();
119 Entry.insert(Entry.begin(), &MI);
|
| /src/external/apache2/llvm/dist/clang/lib/AST/ |
| AttrImpl.cpp | 116 modifiers_iterator MI = modifiers_begin();
119 if (*MI != OMPC_LINEAR_unknown)
120 OS << getOpenMPSimpleClauseTypeName(llvm::omp::Clause::OMPC_linear, *MI)
123 if (*MI != OMPC_LINEAR_unknown)
131 ++MI;
|
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/ |
| CheckObjCInstMethSignature.cpp | 106 MapTy::iterator MI = IMeths.find(S);
108 if (MI == IMeths.end() || MI->second == nullptr)
112 ObjCMethodDecl *MethDerived = MI->second;
113 MI->second = nullptr;
|
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| CheckerHelpers.cpp | 118 const MacroInfo *MI = PP.getMacroInfo(MacroII);
119 if (!MI)
124 FilteredTokens.reserve(MI->tokens().size());
125 for (auto &T : MI->tokens())
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| GISelChangeObserver.h | 36 virtual void erasingInstr(MachineInstr &MI) = 0;
43 virtual void createdInstr(MachineInstr &MI) = 0;
46 virtual void changingInstr(MachineInstr &MI) = 0;
49 virtual void changedInstr(MachineInstr &MI) = 0;
84 void erasingInstr(MachineInstr &MI) override {
86 O->erasingInstr(MI);
88 void createdInstr(MachineInstr &MI) override {
90 O->createdInstr(MI);
92 void changingInstr(MachineInstr &MI) override {
94 O->changingInstr(MI);
[all...] |
| Utils.h | 143 /// Check whether an instruction \p MI is dead: it only defines dead virtual
145 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
156 const MachineInstr &MI);
207 MachineInstr *MI;
327 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
328 /// If \p MI is not a splat, returns None.
329 Optional<int> getSplatIndex(MachineInstr &MI);
332 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI,
337 bool isBuildVectorAllZeros(const MachineInstr &MI,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| CSEMIRBuilder.cpp | 40 MachineInstr *MI =
42 if (MI) {
43 CSEInfo->countOpcodeHit(MI->getOpcode());
45 auto MII = MachineBasicBlock::iterator(MI);
50 } else if (!dominates(MI, CurrPos)) {
51 CurMBB->splice(CurrPos, CurMBB, MI);
53 return MachineInstrBuilder(getMF(), MI);
|
