1 /* $NetBSD: mips_3x30.c,v 1.20 2025/05/01 05:36:02 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define __INTR_PRIVATE 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: mips_3x30.c,v 1.20 2025/05/01 05:36:02 tsutsui Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/kernel.h> 41 #include <sys/cpu.h> 42 #include <sys/intr.h> 43 44 #include <machine/locore.h> 45 #include <machine/trap.h> 46 #include <machine/psl.h> 47 #include <machine/mainboard.h> 48 #include <machine/sysconf.h> 49 50 /* Local functions */ 51 void pizazz_init(void); 52 void pizazz_intr(uint32_t, vaddr_t, uint32_t); 53 int pizazz_level0_intr(void *); 54 void pizazz_level5_intr(uint32_t, vaddr_t); 55 void pizazz_intr_establish (int, int (*)(void *), void *); 56 57 #define INT_MASK_FPU MIPS_INT_MASK_3 58 59 /* 60 * nesting interrupt masks. 61 */ 62 #define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0 63 #define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0) 64 #define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1) 65 #define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0) 66 #define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1) 67 #define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2) 68 #define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3) 69 #define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4) 70 71 const struct ipl_sr_map pizazz_ipl_sr_map = { 72 .sr_bits = { 73 [IPL_NONE] = 0, 74 [IPL_SOFTCLOCK] = MIPS_INT_MASK_SPL_SOFT0, 75 [IPL_SOFTNET] = MIPS_INT_MASK_SPL_SOFT1, 76 [IPL_VM] = MIPS_INT_MASK_SPL2, 77 [IPL_SCHED] = MIPS_INT_MASK_SPL2, 78 [IPL_DDB] = MIPS_INT_MASK, 79 [IPL_HIGH] = MIPS_INT_MASK, 80 }, 81 }; 82 83 void 84 pizazz_init(void) 85 { 86 platform.iobus = "obio"; 87 platform.cons_init = NULL; 88 platform.iointr = pizazz_intr; 89 platform.intr_establish = pizazz_intr_establish; 90 91 ipl_sr_map = pizazz_ipl_sr_map; 92 93 pizazz_intr_establish(SYS_INTR_LEVEL0, pizazz_level0_intr, NULL); 94 95 cpu_setmodel("Mips 3230 Magnum (Pizazz)"); 96 cpuspeed = 25; 97 } 98 99 #define HANDLE_INTR(intr, mask) \ 100 do { \ 101 if (ipending & (mask)) { \ 102 CALL_INTR(intr); \ 103 } \ 104 } while (0) 105 106 void 107 pizazz_intr(uint32_t status, vaddr_t pc, uint32_t ipending) 108 { 109 /* handle clock interrupts ASAP */ 110 if (ipending & MIPS_INT_MASK_2) { /* Timer Interrupt */ 111 void rambo_clkintr (struct clockframe *); 112 struct clockframe cf; 113 114 cf.pc = pc; 115 cf.sr = status; 116 cf.intr = (curcpu()->ci_idepth > 1); 117 118 rambo_clkintr(&cf); 119 } 120 121 if (ipending & MIPS_INT_MASK_5) /* level 5 interrupt */ 122 pizazz_level5_intr(status, pc); 123 124 HANDLE_INTR(SYS_INTR_FDC, MIPS_INT_MASK_4); 125 HANDLE_INTR(SYS_INTR_SCSI, MIPS_INT_MASK_1); 126 HANDLE_INTR(SYS_INTR_LEVEL0, MIPS_INT_MASK_0); 127 128 #if !defined(NOFPU) 129 /* FPU notification */ 130 if (ipending & INT_MASK_FPU) { 131 if (!USERMODE(status)) 132 panic("kernel used FPU: PC %x, SR %x", 133 pc, status); 134 mips_fpu_intr(pc, curlwp->l_md.md_utf); 135 } 136 #endif 137 } 138 139 /* 140 * Level 0 interrupt handler 141 * 142 * Pizazz shares Lance, SCC, Expansion slot and Keyboard on level 0 143 * A secondary interrupt status register shows the real interrupt source 144 */ 145 int 146 pizazz_level0_intr(void *arg) 147 { 148 register int stat; 149 150 /* stat register is active low */ 151 stat = ~*(volatile u_char *)INTREG_0; 152 153 if (stat & INT_ExpSlot) 154 CALL_INTR(SYS_INTR_ATBUS); 155 156 if (stat & INT_Lance) 157 CALL_INTR(SYS_INTR_ETHER); 158 159 if (stat & INT_SCC) 160 CALL_INTR(SYS_INTR_SCC0); 161 162 return 0; 163 } 164 165 /* 166 * Motherboard Parity Error 167 */ 168 void 169 pizazz_level5_intr(uint32_t status, vaddr_t pc) 170 { 171 uint32_t ereg; 172 173 ereg = *(uint32_t *)RAMBO_ERREG; 174 175 printf("interrupt: pc=%p sr=%x\n", (void *)pc, status); 176 printf("parity error: %p mask: 0x%x\n", (void *)ereg, ereg & 0xf); 177 panic("memory fault"); 178 } 179 180 void 181 pizazz_intr_establish(int level, int (*func) (void *), void *arg) 182 { 183 if (level < 0 || level >= MAX_INTR_COOKIES) 184 panic("invalid interrupt level"); 185 186 if (intrtab[level].ih_fun != NULL) 187 panic("cannot share interrupt %d", level); 188 189 intrtab[level].ih_fun = func; 190 intrtab[level].ih_arg = arg; 191 } 192
Indexes created Thu Sep 25 15:09:46 GMT 2025