| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstructionSelector.h | 241 // g_ptr_add (n0, _)
242 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
244 Register N0, N2, N3;
|
| AMDGPUISelDAGToDAG.cpp | 919 SDValue &N0, SDValue &N1) {
940 N0 = BaseLo.getOperand(0).getOperand(0);
1210 SDValue N0 = Addr.getOperand(0);
1213 if (isDSOffsetLegal(N0, C1->getSExtValue())) {
1214 // (add n0, c0)
1215 Base = N0;
1314 SDValue N0 = Addr.getOperand(0);
1320 // (add n0, c0)
1321 if (isDSOffset2Legal(N0, OffsetValue0, OffsetValue1, Size)) {
1322 Base = N0;
[all...] |
| AMDGPUISelLowering.cpp | 2615 SDValue N0 = Op.getOperand(0);
2618 if (N0.getValueType() == MVT::f32)
2619 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
2626 assert(N0.getSimpleValueType() == MVT::f64);
2634 SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);
2980 SDValue N0 = N->getOperand(0);
2984 if (N0.getOpcode() == ISD::TRUNCATE) {
2989 SDValue Src = N0.getOperand(0);
3289 SDValue N0, SDValue N1, unsigned Size, bool Signed) {
3292 return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1)
[all...] |
| SIISelLowering.cpp | 7816 SDValue N0 = Offset;
7819 if ((C1 = dyn_cast<ConstantSDNode>(N0)))
7820 N0 = SDValue();
7821 else if (DAG.isBaseWithConstantOffset(N0)) {
7822 C1 = cast<ConstantSDNode>(N0.getOperand(1));
7823 N0 = N0.getOperand(0);
7844 if (!N0)
7845 N0 = OverflowVal;
7847 SDValue Ops[] = { N0, OverflowVal }
[all...] |
| /src/external/lgpl3/mpfr/dist/tests/ |
| tprintf.c | 552 #define N0 20
554 for (i = 1; i <= N0; i++)
556 char s[N0+4];
|
| tsprintf.c | 68 int n0, n1; local
72 n0 = mpfr_sprintf (buffer, fmt, x);
82 randsize = (int) (randlimb () % (n0 + 3)) - 3; /* between -3 and n0 - 1 */
98 if (n0 != n1)
102 printf ("expected: %d\ngot: %d\nx='", n0, n1);
126 int n0, n1; local
131 n0 = mpfr_vsprintf (buffer, fmt, ap0);
144 randsize = (int) (randlimb () % (n0 + 3)) - 3; /* between -3 and n0 - 1 *
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 1445 SDValue N0 = N->getOperand(0);
1447 if (N0.getNode()->hasOneUse())
1448 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1451 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1459 SDValue N0 = N->getOperand(0);
1464 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelDAGToDAG.cpp | 412 SDValue N0 = Node->getOperand(0);
413 if (ShAmt < 16 && N0.getOpcode() == ISD::AND && N0.hasOneUse() &&
414 isa<ConstantSDNode>(N0.getOperand(1))) {
415 uint64_t Mask = N0.getConstantOperandVal(1);
420 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
|
| RISCVISelLowering.cpp | 5469 SDValue N0 = N->getOperand(0);
5471 if (SDValue Result = combineSelectCCAndUse(N, N0, N1, DAG, AllOnes))
5473 if (SDValue Result = combineSelectCCAndUse(N, N1, N0, DAG, AllOnes))
5934 SDValue N0 = N->getOperand(0);
5935 EVT Ty = N0.getValueType();
5937 (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
5938 auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 583 SDValue N0 = Op.getOperand(0);
587 if (N0.getOpcode() == ISD::ADD) {
588 AddOp = N0;
592 OtherOp = N0;
1634 SDValue N0 = N->getOperand(0);
1637 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1639 EVT VT = N0.getValueType();
1643 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1662 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1670 SDValue N0 = N->getOperand(0)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 1002 SDValue N0 = I->getOperand(0), N1 = I->getOperand(1);
1004 bool SelN0 = IsSelect0(N0);
1005 SDValue SOp = SelN0 ? N0 : N1;
1006 SDValue VOp = SelN0 ? N1 : N0;
1394 SDValue N0 = N.getOperand(0);
1396 unsigned GAOpc = N0.getOpcode();
1404 SDValue Addr = N0.getOperand(0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 4312 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4315 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4321 EVT VT=N0.getValueType();
4327 if (N0.getOpcode() == ISD::MUL) {
4334 !N0.getNode()->hasOneUse())
4339 N0.getOperand(0), N0.getOperand(1), N1);
4341 else if (N0.getOpcode() == ISD::FMUL) {
4358 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4359 UE = N0.getNode()->use_end()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 419 SDValue N0 = N->getOperand(0);
423 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
424 std::swap(N0, N1);
459 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1))
462 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
463 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
477 CurDAG->UpdateNodeOperands(N, N0, N1);
3678 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3682 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse())
[all...] |
| ARMISelLowering.cpp | 8965 SDNode *N0 = N->getOperand(0).getNode();
8967 return N0->hasOneUse() && N1->hasOneUse() &&
8968 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
8976 SDNode *N0 = N->getOperand(0).getNode();
8978 return N0->hasOneUse() && N1->hasOneUse() &&
8979 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
8990 SDNode *N0 = Op.getOperand(0).getNode();
8994 bool isN0SExt = isSignExtended(N0, DAG);
8999 bool isN0ZExt = isZeroExtended(N0, DAG);
9006 if (isN1SExt && isAddSubSExt(N0, DAG))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 1367 SDValue N0 = N->getOperand(0);
1370 if (!N0.isMachineOpcode() ||
1371 N0.getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG ||
1372 N0.getConstantOperandVal(1) != X86::sub_8bit)
1378 SDValue N00 = N0.getOperand(0);
1690 SDValue N0 = N.getOperand(0);
1691 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
1695 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
1700 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
1703 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 2931 SDValue N0 = N->getOperand(0);
2932 GetExpandedInteger(N0, Lo, Hi);
2959 DAG.getConstant(0, dl, VT), N0);
|
| LegalizeVectorTypes.cpp | 1379 SDValue N0 = N->getOperand(0);
1384 if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
1385 GetSplitVector(N0, InLo, InHi);
|
| TargetLowering.cpp | 3027 TargetLowering::buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
3032 std::swap(N0, N1);
3040 return DAG.getVectorShuffle(VT, DL, N0, N1, Mask);
3141 SDValue TargetLowering::foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
3147 if (N1.getOpcode() == ISD::AND && N0.getOpcode() != ISD::AND)
3148 std::swap(N0, N1);
3150 EVT OpVT = N0.getValueType();
3151 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() ||
3156 if (N0.getOperand(0) == N1) {
3157 X = N0.getOperand(1)
[all...] |
| DAGCombiner.cpp | 404 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
410 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
416 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
424 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
426 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
435 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
437 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
525 const SDLoc &DL, SDValue N0,
527 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
529 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 5868 SDValue N0 = N->getOperand(0);
5870 if (N0.getOpcode() == SystemZISD::SELECT_CCMASK) {
5871 auto *TrueOp = dyn_cast<ConstantSDNode>(N0.getOperand(0));
5872 auto *FalseOp = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5874 SDLoc DL(N0);
5877 N0.getOperand(2), N0.getOperand(3), N0.getOperand(4) };
5879 // If N0 has multiple uses, change other uses as well.
5880 if (!N0.hasOneUse())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 9660 SDValue N0 = peekThroughBitcasts(Op.getOperand(0));
9668 DAG.getVectorShuffle(MVT::v16i8, dl, DAG.getBitcast(MVT::v16i8, N0),
9672 SDValue ArgVal = DAG.getBitcast(MVT::i128, N0);
15400 SDValue N0 = N->getOperand(0);
15406 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
16354 SDValue N0 = Op.getOperand(0);
16373 SDValue NegN0 = getNegatedExpression(N0, DAG, LegalOps, OptForSize,
16385 return DAG.getNode(Opc, Loc, VT, N0, NegN1, NegN2, Flags);
16392 return DAG.getNode(ISD::FMA, Loc, VT, N0, N1, NegN2, Flags);
16441 SDValue N0 = N->getOperand(0)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 3581 SDNode *N0 = N->getOperand(0).getNode();
3583 return N0->hasOneUse() && N1->hasOneUse() &&
3584 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
3592 SDNode *N0 = N->getOperand(0).getNode();
3594 return N0->hasOneUse() && N1->hasOneUse() &&
3595 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
3680 SDNode *N0 = Op.getOperand(0).getNode();
3684 bool isN0SExt = isSignExtended(N0, DAG);
3689 bool isN0ZExt = isZeroExtended(N0, DAG);
3696 if (isN1SExt && isAddSubSExt(N0, DAG))
[all...] |
