1 /* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator. 2 Copyright (C) 1994 Advanced RISC Machines Ltd. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 3 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 16 17 #include "armdefs.h" 18 19 extern ARMword isize; 20 extern int trace; 21 extern int disas; 22 extern int trace_funcs; 23 extern void print_insn (ARMword); 24 25 /* Condition code values. */ 26 #define EQ 0 27 #define NE 1 28 #define CS 2 29 #define CC 3 30 #define MI 4 31 #define PL 5 32 #define VS 6 33 #define VC 7 34 #define HI 8 35 #define LS 9 36 #define GE 10 37 #define LT 11 38 #define GT 12 39 #define LE 13 40 #define AL 14 41 #define NV 15 42 43 /* Shift Opcodes. */ 44 #define LSL 0 45 #define LSR 1 46 #define ASR 2 47 #define ROR 3 48 49 /* Macros to twiddle the status flags and mode. */ 50 #define NBIT ((unsigned)1L << 31) 51 #define ZBIT (1L << 30) 52 #define CBIT (1L << 29) 53 #define VBIT (1L << 28) 54 #define SBIT (1L << 27) 55 #define GE0 (1L << 16) 56 #define GE1 (1L << 17) 57 #define GE2 (1L << 18) 58 #define GE3 (1L << 19) 59 #define IBIT (1L << 7) 60 #define FBIT (1L << 6) 61 #define IFBITS (3L << 6) 62 #define R15IBIT (1L << 27) 63 #define R15FBIT (1L << 26) 64 #define R15IFBITS (3L << 26) 65 66 #define POS(i) ( (~(i)) >> 31 ) 67 #define NEG(i) ( (i) >> 31 ) 68 69 #ifdef MODET /* Thumb support. */ 70 /* ??? This bit is actually in the low order bit of the PC in the hardware. 71 It isn't clear if the simulator needs to model that or not. */ 72 #define TBIT (1L << 5) 73 #define TFLAG state->TFlag 74 #define SETT state->TFlag = 1 75 #define CLEART state->TFlag = 0 76 #define ASSIGNT(res) state->TFlag = res 77 #define INSN_SIZE (TFLAG ? 2 : 4) 78 #else 79 #define INSN_SIZE 4 80 #endif 81 82 #define NFLAG state->NFlag 83 #define SETN state->NFlag = 1 84 #define CLEARN state->NFlag = 0 85 #define ASSIGNN(res) state->NFlag = res 86 87 #define ZFLAG state->ZFlag 88 #define SETZ state->ZFlag = 1 89 #define CLEARZ state->ZFlag = 0 90 #define ASSIGNZ(res) state->ZFlag = res 91 92 #define CFLAG state->CFlag 93 #define SETC state->CFlag = 1 94 #define CLEARC state->CFlag = 0 95 #define ASSIGNC(res) state->CFlag = res 96 97 #define VFLAG state->VFlag 98 #define SETV state->VFlag = 1 99 #define CLEARV state->VFlag = 0 100 #define ASSIGNV(res) state->VFlag = res 101 102 #define SFLAG state->SFlag 103 #define SETS state->SFlag = 1 104 #define CLEARS state->SFlag = 0 105 #define ASSIGNS(res) state->SFlag = res 106 107 #define IFLAG (state->IFFlags >> 1) 108 #define FFLAG (state->IFFlags & 1) 109 #define IFFLAGS state->IFFlags 110 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3) 111 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ; 112 113 #define PSR_FBITS (0xff000000L) 114 #define PSR_SBITS (0x00ff0000L) 115 #define PSR_XBITS (0x0000ff00L) 116 #define PSR_CBITS (0x000000ffL) 117 118 #if defined MODE32 || defined MODET 119 #define CCBITS (0xf8000000L) 120 #else 121 #define CCBITS (0xf0000000L) 122 #endif 123 124 #define INTBITS (0xc0L) 125 126 #if defined MODET && defined MODE32 127 #define PCBITS (0xffffffffL) 128 #else 129 #define PCBITS (0xfffffffcL) 130 #endif 131 132 #define MODEBITS (0x1fL) 133 #define R15INTBITS (3L << 26) 134 135 #if defined MODET && defined MODE32 136 #define R15PCBITS (0x03ffffffL) 137 #else 138 #define R15PCBITS (0x03fffffcL) 139 #endif 140 141 #define R15PCMODEBITS (0x03ffffffL) 142 #define R15MODEBITS (0x3L) 143 144 #ifdef MODE32 145 #define PCMASK PCBITS 146 #define PCWRAP(pc) (pc) 147 #else 148 #define PCMASK R15PCBITS 149 #define PCWRAP(pc) ((pc) & R15PCBITS) 150 #endif 151 152 #define PC (state->Reg[15] & PCMASK) 153 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) 154 #define R15INT (state->Reg[15] & R15INTBITS) 155 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) 156 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS)) 157 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS)) 158 #define R15PC (state->Reg[15] & R15PCBITS) 159 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS)) 160 #define R15MODE (state->Reg[15] & R15MODEBITS) 161 162 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27)) 163 #define EINT (IFFLAGS << 6) 164 #define ER15INT (IFFLAGS << 26) 165 #define EMODE (state->Mode) 166 167 #ifdef MODET 168 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) 169 #else 170 #define CPSR (ECC | EINT | EMODE) 171 #endif 172 173 #ifdef MODE32 174 #define PATCHR15 175 #else 176 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC 177 #endif 178 179 #define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE)) 180 #define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS) 181 #define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS) 182 #define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS) 183 #define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS) 184 185 #define SETR15PSR(s) \ 186 do \ 187 { \ 188 if (state->Mode == USER26MODE) \ 189 { \ 190 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \ 191 ASSIGNN ((state->Reg[15] & NBIT) != 0); \ 192 ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \ 193 ASSIGNC ((state->Reg[15] & CBIT) != 0); \ 194 ASSIGNV ((state->Reg[15] & VBIT) != 0); \ 195 } \ 196 else \ 197 { \ 198 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \ 199 ARMul_R15Altered (state); \ 200 } \ 201 } \ 202 while (0) 203 204 #define SETABORT(i, m, d) \ 205 do \ 206 { \ 207 int SETABORT_mode = (m); \ 208 \ 209 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \ 210 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \ 211 | (i) | SETABORT_mode)); \ 212 state->Reg[14] = temp - (d); \ 213 } \ 214 while (0) 215 216 #ifndef MODE32 217 #define VECTORS 0x20 218 #define LEGALADDR 0x03ffffff 219 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig) 220 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig) 221 #endif 222 223 #define INTERNALABORT(address) \ 224 do \ 225 { \ 226 if (address < VECTORS) \ 227 state->Aborted = ARMul_DataAbortV; \ 228 else \ 229 state->Aborted = ARMul_AddrExceptnV; \ 230 } \ 231 while (0) 232 233 #ifdef MODE32 234 #define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV) 235 #else 236 #define TAKEABORT \ 237 do \ 238 { \ 239 if (state->Aborted == ARMul_AddrExceptnV) \ 240 ARMul_Abort (state, ARMul_AddrExceptnV); \ 241 else \ 242 ARMul_Abort (state, ARMul_DataAbortV); \ 243 } \ 244 while (0) 245 #endif 246 247 #define CPTAKEABORT \ 248 do \ 249 { \ 250 if (!state->Aborted) \ 251 ARMul_Abort (state, ARMul_UndefinedInstrV); \ 252 else if (state->Aborted == ARMul_AddrExceptnV) \ 253 ARMul_Abort (state, ARMul_AddrExceptnV); \ 254 else \ 255 ARMul_Abort (state, ARMul_DataAbortV); \ 256 } \ 257 while (0); 258 259 260 /* Different ways to start the next instruction. */ 261 #define SEQ 0 262 #define NONSEQ 1 263 #define PCINCEDSEQ 2 264 #define PCINCEDNONSEQ 3 265 #define PRIMEPIPE 4 266 #define RESUME 8 267 268 #define NORMALCYCLE state->NextInstr = 0 269 #define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */ 270 #define BUSUSEDINCPCS \ 271 do \ 272 { \ 273 if (! state->is_v4) \ 274 { \ 275 /* A standard PC inc and an S cycle. */ \ 276 state->Reg[15] += isize; \ 277 state->NextInstr = (state->NextInstr & 0xff) | 2; \ 278 } \ 279 } \ 280 while (0) 281 282 #define BUSUSEDINCPCN \ 283 do \ 284 { \ 285 if (state->is_v4) \ 286 BUSUSEDN; \ 287 else \ 288 { \ 289 /* A standard PC inc and an N cycle. */ \ 290 state->Reg[15] += isize; \ 291 state->NextInstr |= 3; \ 292 } \ 293 } \ 294 while (0) 295 296 #define INCPC \ 297 do \ 298 { \ 299 /* A standard PC inc. */ \ 300 state->Reg[15] += isize; \ 301 state->NextInstr |= 2; \ 302 } \ 303 while (0) 304 305 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE 306 307 /* Cycle based emulation. */ 308 309 #define OUTPUTCP(i,a,b) 310 #define NCYCLE 311 #define SCYCLE 312 #define ICYCLE 313 #define CCYCLE 314 #define NEXTCYCLE(c) 315 316 /* Macros to extract parts of instructions. */ 317 #define DESTReg (BITS (12, 15)) 318 #define LHSReg (BITS (16, 19)) 319 #define RHSReg (BITS ( 0, 3)) 320 321 #define DEST (state->Reg[DESTReg]) 322 323 #ifdef MODE32 324 #ifdef MODET 325 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg])) 326 #else 327 #define LHS (state->Reg[LHSReg]) 328 #endif 329 #else 330 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg])) 331 #endif 332 333 #define MULDESTReg (BITS (16, 19)) 334 #define MULLHSReg (BITS ( 0, 3)) 335 #define MULRHSReg (BITS ( 8, 11)) 336 #define MULACCReg (BITS (12, 15)) 337 338 #define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)]) 339 #define DPSImmRHS temp = BITS(0,11) ; \ 340 rhs = ARMul_ImmedTable[temp] ; \ 341 if (temp > 255) /* There was a shift. */ \ 342 ASSIGNC (rhs >> 31) ; 343 344 #ifdef MODE32 345 #define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ 346 : GetDPRegRHS (state, instr)) 347 #define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ 348 : GetDPSRegRHS (state, instr)) 349 #else 350 #define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 351 : GetDPRegRHS (state, instr)) 352 #define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 353 : GetDPSRegRHS (state, instr)) 354 #endif 355 356 #define LSBase state->Reg[LHSReg] 357 #define LSImmRHS (BITS(0,11)) 358 359 #ifdef MODE32 360 #define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \ 361 : GetLSRegRHS (state, instr)) 362 #else 363 #define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 364 : GetLSRegRHS (state, instr)) 365 #endif 366 367 #define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \ 368 (ARMword) ARMul_BitList[BITS (8, 15)] ) 369 #define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \ 370 (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0)) 371 372 #define SWAPSRC (state->Reg[RHSReg]) 373 374 #define LSCOff (BITS (0, 7) << 2) 375 #define CPNum BITS (8, 11) 376 377 /* Determine if access to coprocessor CP is permitted. 378 The XScale has a register in CP15 which controls access to CP0 - CP13. */ 379 #define CP_ACCESS_ALLOWED(STATE, CP) \ 380 ( ((CP) >= 14) \ 381 || (! (STATE)->is_XScale) \ 382 || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) 383 384 /* Macro to rotate n right by b bits. */ 385 #define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) 386 387 /* Macros to store results of instructions. */ 388 #define WRITEDEST(d) \ 389 do \ 390 { \ 391 if (DESTReg == 15) \ 392 WriteR15 (state, d); \ 393 else \ 394 DEST = d; \ 395 } \ 396 while (0) 397 398 #define WRITESDEST(d) \ 399 do \ 400 { \ 401 if (DESTReg == 15) \ 402 WriteSR15 (state, d); \ 403 else \ 404 { \ 405 DEST = d; \ 406 ARMul_NegZero (state, d); \ 407 } \ 408 } \ 409 while (0) 410 411 #define WRITEDESTB(d) \ 412 do \ 413 { \ 414 if (DESTReg == 15) \ 415 WriteR15Load (state, d); \ 416 else \ 417 DEST = d; \ 418 } \ 419 while (0) 420 421 #define BYTETOBUS(data) ((data & 0xff) | \ 422 ((data & 0xff) << 8) | \ 423 ((data & 0xff) << 16) | \ 424 ((data & 0xff) << 24)) 425 426 #define BUSTOBYTE(address, data) \ 427 do \ 428 { \ 429 if (state->bigendSig) \ 430 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \ 431 else \ 432 temp = (data >> ((address & 3) << 3)) & 0xff; \ 433 } \ 434 while (0) 435 436 #define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb) 437 #define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb) 438 #define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb) 439 #define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb) 440 441 #define POSBRANCH ((instr & 0x7fffff) << 2) 442 #define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2) 443 444 445 /* Values for Emulate. */ 446 #define STOP 0 /* stop */ 447 #define CHANGEMODE 1 /* change mode */ 448 #define ONCE 2 /* execute just one interation */ 449 #define RUN 3 /* continuous execution */ 450 451 /* Stuff that is shared across modes. */ 452 extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */ 453 extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */ 454 extern char ARMul_BitList[]; /* Number of bits in a byte table. */ 455 456 #define EVENTLISTSIZE 1024L 457 458 /* Thumb support. */ 459 typedef enum 460 { 461 t_undefined, /* Undefined Thumb instruction. */ 462 t_decoded, /* Instruction decoded to ARM equivalent. */ 463 t_branch /* Thumb branch (already processed). */ 464 } 465 tdstate; 466 467 #define t_resolved t_branch 468 469 /* Macros to scrutinize instructions. The dummy do loop is to keep the compiler 470 happy when the statement is used in an otherwise empty else statement. */ 471 #define UNDEF_Test do { ; } while (0) 472 #define UNDEF_Shift do { ; } while (0) 473 #define UNDEF_MSRPC do { ; } while (0) 474 #define UNDEF_MRSPC do { ; } while (0) 475 #define UNDEF_MULPCDest do { ; } while (0) 476 #define UNDEF_MULDestEQOp1 do { ; } while (0) 477 #define UNDEF_LSRBPC do { ; } while (0) 478 #define UNDEF_LSRBaseEQOffWb do { ; } while (0) 479 #define UNDEF_LSRBaseEQDestWb do { ; } while (0) 480 #define UNDEF_LSRPCBaseWb do { ; } while (0) 481 #define UNDEF_LSRPCOffWb do { ; } while (0) 482 #define UNDEF_LSMNoRegs do { ; } while (0) 483 #define UNDEF_LSMPCBase do { ; } while (0) 484 #define UNDEF_LSMUserBankWb do { ; } while (0) 485 #define UNDEF_LSMBaseInListWb do { ; } while (0) 486 #define UNDEF_SWPPC do { ; } while (0) 487 #define UNDEF_CoProHS do { ; } while (0) 488 #define UNDEF_MCRPC do { ; } while (0) 489 #define UNDEF_LSCPCBaseWb do { ; } while (0) 490 #define UNDEF_UndefNotBounced do { ; } while (0) 491 #define UNDEF_ShortInt do { ; } while (0) 492 #define UNDEF_IllegalMode do { ; } while (0) 493 #define UNDEF_Prog32SigChange do { ; } while (0) 494 #define UNDEF_Data32SigChange do { ; } while (0) 495 496 /* Prototypes for exported functions. */ 497 extern unsigned ARMul_NthReg (ARMword, unsigned); 498 extern int AddOverflow (ARMword, ARMword, ARMword); 499 extern int SubOverflow (ARMword, ARMword, ARMword); 500 extern ARMword ARMul_Emulate26 (ARMul_State *); 501 extern ARMword ARMul_Emulate32 (ARMul_State *); 502 extern unsigned IntPending (ARMul_State *); 503 extern void ARMul_CPSRAltered (ARMul_State *); 504 extern void ARMul_R15Altered (ARMul_State *); 505 extern ARMword ARMul_GetPC (ARMul_State *); 506 extern ARMword ARMul_GetNextPC (ARMul_State *); 507 extern ARMword ARMul_GetR15 (ARMul_State *); 508 extern ARMword ARMul_GetCPSR (ARMul_State *); 509 extern void ARMul_EnvokeEvent (ARMul_State *); 510 extern unsigned long ARMul_Time (ARMul_State *); 511 extern void ARMul_NegZero (ARMul_State *, ARMword); 512 extern void ARMul_SetPC (ARMul_State *, ARMword); 513 extern void ARMul_SetR15 (ARMul_State *, ARMword); 514 extern void ARMul_SetCPSR (ARMul_State *, ARMword); 515 extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword); 516 extern void ARMul_Abort26 (ARMul_State *, ARMword); 517 extern void ARMul_Abort32 (ARMul_State *, ARMword); 518 extern ARMword ARMul_MRC (ARMul_State *, ARMword); 519 extern void ARMul_CDP (ARMul_State *, ARMword); 520 extern void ARMul_LDC (ARMul_State *, ARMword, ARMword); 521 extern void ARMul_STC (ARMul_State *, ARMword, ARMword); 522 extern void ARMul_MCR (ARMul_State *, ARMword, ARMword); 523 extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword); 524 extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); 525 extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword); 526 extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); 527 extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword); 528 extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword); 529 extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword); 530 extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword); 531 extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword); 532 extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); 533 extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); 534 extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); 535 extern void ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *)); 536 /* Coprocessor support functions. */ 537 extern unsigned ARMul_CoProInit (ARMul_State *); 538 extern void ARMul_CoProExit (ARMul_State *); 539 extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *, 540 ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *, 541 ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *); 542 extern void ARMul_CoProDetach (ARMul_State *, unsigned); 543 extern ARMword read_cp15_reg (unsigned, unsigned, unsigned); 544 545 extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword); 546 extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword); 547 extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *); 548 extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *); 549 extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword); 550 extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword); 551 extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *); 552 extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword); 553 extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *); 554 extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword); 555 extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword); 556 extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *); 557 extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword); 558
Indexes created Sun Jun 07 00:24:08 UTC 2026