| /src/external/apache2/llvm/dist/clang/lib/Analysis/ |
| ThreadSafetyCommon.cpp | 166 bool Neg = false;
169 Neg = true;
175 Neg = true;
190 return CapabilityExpr(CE->expr(), Neg);
192 return CapabilityExpr(E, Neg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIPeepholeSDWA.cpp | 118 bool Neg;
126 SrcSel(SrcSel_), Abs(Abs_), Neg(Neg_), Sext(Sext_) {}
133 bool getNeg() const { return Neg; }
225 << " abs:" << getAbs() << " neg:" << getNeg()
317 if (Abs || Neg) {
321 Mods ^= Neg ? SISrcMods::NEG : 0u;
|
| R600ISelLowering.cpp | 1981 SDValue &Src, SDValue &Neg, SDValue &Abs,
1990 if (!Neg.getNode())
1993 Neg = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32);
2157 SDValue &Neg = Ops[NegIdx[i] - 1];
2164 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2195 SDValue &Neg = Ops[NegIdx[i] - 1];
2207 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
|
| AMDGPUISelLowering.cpp | 2107 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags);
2109 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags);
3525 // Careful: if the neg can be folded up, don't try to pull it back down.
3786 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res);
3787 DAG.ReplaceAllUsesWith(N0, Neg);
3789 for (SDNode *U : Neg->uses())
3817 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3818 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
3833 SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
3834 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 276 Value *Neg = dyn_castNegVal(Y);
278 (Div->getOperand(1) == Y || Div->getOperand(1) == Neg) &&
1132 AShr->setName(I.getName() + ".neg");
|
| InstCombineAddSub.cpp | 764 // ADD(XOR(OR(Z, NOT(C)), C)), 1) == NEG(AND(Z, C))
765 // ADD(XOR(AND(Z, C), C), 1) == NEG(OR(Z, ~C))
766 // XOR(AND(Z, C), (C + 1)) == NEG(OR(Z, ~C)) if C is even
812 // LHS = XOR(Y, C1), Y = AND(Z, C2), C1 == (C2 + 1) => LHS == NEG(OR(Z, ~C2))
1705 Result = Builder.CreateNeg(Result, "diff.neg");
1913 // (sub (and A, B) (or A, B)) --> neg (xor A, B)
1930 // (sub (xor A, B) (or A, B)) --> neg (and A, B)
1948 // (sub (and Op1, (neg X)), Op1) --> neg (and Op1, (add X, -1))
1958 // (sub (and Op1, C), Op1) --> neg (and Op1, ~C
[all...] |
| InstCombineAndOrXor.cpp | 3229 Value *Neg = Builder.CreateNeg(A, "", Add->hasNoUnsignedWrap(),
3231 return SelectInst::Create(Cmp, Neg, A);
|
| InstCombineCompares.cpp | 2452 } else { // (X / pos) op neg
2464 if (C.isNullValue()) { // (X / neg) op 0
2472 } else if (C.isStrictlyPositive()) { // (X / neg) op pos
2478 } else { // (X / neg) op neg
3022 Value *Neg = Builder.CreateNeg(BOp1);
3023 Neg->takeName(BO);
3024 return new ICmpInst(Pred, BOp0, Neg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonConstExtenders.cpp | 293 bool Neg = false;
296 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {}
302 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;
312 return !Neg && Ex.Neg;
467 OS << "## " << (P.Ex.Neg ? "- " : "+ ");
1206 ED.Expr.Neg = true;
1210 ED.Expr.Neg = true;
1540 assert(!Ex.Neg && "Cannot subtract a stack slot")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| AutoUpgrade.cpp | 3599 Value *Neg = Builder.CreateNeg(Arg, "neg");
3602 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs");
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 2800 // generate a NEG instead of a SUB of a constant.
2817 MachineSDNode *Neg =
2819 NewShiftAmt = SDValue(Neg, 0);
|
| AArch64ISelLowering.cpp | 1901 MAKE_CASE(AArch64ISD::NEG)
2477 /// - We can implement (NEG SETCC) i.e. negating a single comparison by
2481 /// NEG (CMP CCMP CCCMP ...) can be implemented.
2488 /// NEG (AND (NEG (SETCC A)) (NEG (SETCC B)))
2489 /// - After transforming OR to NEG/AND combinations we may be able to use NEG
4447 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
4453 return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 2049 // (select (x != 0), -1, 0) -> neg & sbb
2050 // (select (x == 0), 0, -1) -> neg & sbb
2056 SDValue Neg =
2062 SDValue(Neg.getNode(), 1));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 282 SDValue Neg = SDValue(CurDAG->getMachineNode(NegOpc, DL, VT, MVT::i32,
284 AM.IndexReg = Neg;
2309 // transformation incurs an extra mov, due to the neg instruction
3855 // to generate a NEG instead of a SUB of a constant.
3879 SDValue Neg = CurDAG->getNode(ISD::SUB, DL, SubVT, Zero, X);
3880 NewShiftAmt = Neg;
3885 insertDAGNode(*CurDAG, OrigShiftAmt, Neg);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetLowering.h | 3645 SDValue Neg =
3647 if (Neg && Cost == NegatibleCost::Cheaper)
3648 return Neg;
3650 if (Neg && Neg.getNode()->use_empty())
3651 DAG.RemoveDeadNode(Neg.getNode());
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 2958 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
2961 SplitInteger(Neg, NegLo, NegHi);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 3010 Register Neg = MRI.createGenericVirtualRegister(Ty);
3011 MIRBuilder.buildFNeg(Neg, RHS);
3012 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
5535 auto Neg = MIRBuilder.buildSub(AmtTy, Zero, Amt);
5536 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg});
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 71 bool Neg = false;
74 bool hasFPModifiers() const { return Abs || Neg; }
81 Operand |= Neg ? SISrcMods::NEG : 0u;
1108 OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;
1949 if (Imm.Mods.Neg) {
2834 return str == "abs" || str == "neg" || str == "sext";
2860 // neg(...)
2881 // Check if the current token is an SP3 'neg' modifier
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 16826 SDValue Neg = DAG.getNode(ISD::USUBO, dl, VTs, FalseVal, Sub);
16831 DAG.getConstant(1, dl, MVT::i32), Neg.getValue(1));
16832 Res = DAG.getNode(ISD::ADDCARRY, dl, VTs, Sub, Neg, Carry);
|
