| /src/external/cddl/osnet/dist/lib/libdtrace/arm/ |
| dt_isadep.c | 47 #define OP2(x) (((x) >> 22) & 0x07)
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| /src/external/cddl/osnet/dist/lib/libdtrace/sparc/ |
| dt_isadep.c | 39 #define OP2(x) (((x) >> 22) & 0x07) 196 switch (OP2(text[i])) {
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| /src/sys/arch/sparc/sparc/ |
| db_disasm.c | 69 * 0000 0001 1100 0000 0000 0000 0000 0000 op2 field, format 2 only 76 #define OP2(x) (((x) & 0x7) << 22) 106 #define FORMAT2(a,b) (OP(a) | OP2(b))
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| /src/sys/arch/sparc64/sparc64/ |
| db_disasm.c | 74 * 0000 0001 1100 0000 0000 0000 0000 0000 op2 field, format 2 only 81 #define OP2(x) (((x) & 0x7) << 22) 111 #define FORMAT2(a,b) (OP(a) | OP2(b))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 265 SDValue OP2 = LDAddrNode->getOperand(1); 276 const ConstantSDNode *CDN = dyn_cast<ConstantSDNode>(OP2.getNode());
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| /src/external/gpl3/gdb.old/dist/sim/pru/ |
| interp.c | 546 uint32_t _RDVAL, OP2; /* intermediate values. */
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| /src/external/gpl3/gdb/dist/sim/pru/ |
| interp.c | 546 uint32_t _RDVAL, OP2; /* intermediate values. */
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| /src/external/gpl3/binutils/dist/include/opcode/ |
| tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG1, OWREG2) [all...] |
| sparc.h | 290 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 303 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG1, OWREG2) [all...] |
| sparc.h | 290 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 303 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG1, OWREG2) [all...] |
| sparc.h | 290 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 303 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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| /src/external/gpl3/gdb/dist/include/opcode/ |
| tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b } 134 OP2(ORXREG1, OWREG1), 139 OP2(ORREGL1, OWREGL1), 144 OP2(ORXREG1, OWREG1), 150 OP2(ORREGD1, OWREGD12), 156 OP2(ORXREG1, OWREG1), 355 OP2(OLCST, OWREG1), 361 OP2(OACST, OWREG1), 513 OP2(OLCST, ORWREG1), 518 OP2(ORXREG1, OWREG2) [all...] |
| sparc.h | 290 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ 303 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600Defines.h | 39 OP2 = (1 << 11),
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| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-rx.c | 2274 #define OP2(x) op[target_big_endian ? 1-x : x] 2308 OP2(1) = val & 0xff; 2309 OP2(0) = (val >> 8) & 0xff; 2351 OP2(0) = val & 0xff; 2352 OP2(1) = (val >> 8) & 0xff;
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| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-rx.c | 2274 #define OP2(x) op[target_big_endian ? 1-x : x] 2308 OP2(1) = val & 0xff; 2309 OP2(0) = (val >> 8) & 0xff; 2351 OP2(0) = val & 0xff; 2352 OP2(1) = (val >> 8) & 0xff;
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| /src/external/gpl3/binutils/dist/opcodes/ |
| aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} 73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ 79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ 85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */ 3647 OP2 (MOPS_ADDR_Rd, MOPS_WB_Rn), QL_I2SAMEX, FLAGS, \ 3694 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3696 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3700 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3703 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3706 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF) [all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} 73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ 79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ 85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */ 3474 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3476 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3480 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3483 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3486 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF), 3488 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF) [all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} 73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ 79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ 85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */ 3236 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3238 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3242 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3245 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3248 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF), 3250 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF) [all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| aarch64-tbl.h | 33 #define OP2(a,b) {OPND(a), OPND(b)} 73 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */ 79 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */ 85 /* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */ 3474 CORE_INSN ("ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3476 CORE_INSN ("ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF), 3480 CORE_INSN ("cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3483 CORE_INSN ("cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_SUBCLASS_OTHER | F_ALIAS | F_SF), 3486 CORE_INSN ("mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ARITH_MOV | F_ALIAS | F_SF), 3488 CORE_INSN ("cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_SUBCLASS_OTHER | F_ALIAS | F_SF) [all...] |