| /src/sys/arch/sparc/sparc/ |
| db_disasm.c | 70 * 0000 0001 1111 1000 0000 0000 0000 0000 op3 field, format 3 only
77 #define OP3(x) (((x) & 0x3f) << 19)
107 #define FORMAT3(a,b,c) (OP(a) | OP3(b) | F3I(c))
108 #define FORMAT3F(a,b,c) (OP(a) | OP3(b) | OPF(c))
110 /* Helper macros to construct OP3 & OPF */
436 * OP3 = (3,10): TCC: Trap on Integer Condition Codes
488 * OP3 = (2,12): MOVcc, Move Integer Register on Condition
584 * OP3 = (2,15): MOVr:
727 * OP3 = (3,4): FPop1 (table 34)
783 * OP3 =(3,5): FPop2 (table 35
[all...] |
| /src/sys/arch/sparc64/sparc64/ |
| db_disasm.c | 75 * 0000 0001 1111 1000 0000 0000 0000 0000 op3 field, format 3 only
82 #define OP3(x) (((x) & 0x3f) << 19)
112 #define FORMAT3(a,b,c) (OP(a) | OP3(b) | F3I(c))
113 #define FORMAT3F(a,b,c) (OP(a) | OP3(b) | OPF(c))
115 /* Helper macros to construct OP3 & OPF */
441 * OP3 = (3,10): TCC: Trap on Integer Condition Codes
493 * OP3 = (2,12): MOVcc, Move Integer Register on Condition
589 * OP3 = (2,15): MOVr:
732 * OP3 = (3,4): FPop1 (table 34)
788 * OP3 =(3,5): FPop2 (table 35
[all...] |
| /src/external/gpl3/binutils/dist/include/opcode/ |
| tic6x-opcode-table.h | 44 #define OP3(a, b, c) 3, { a, b, c }
162 OP3(ORREG1, ORXREG1, OWREG1),
167 OP3(ORREG1, ORXREG1, OWREGL1),
172 OP3(ORXREG1, ORREGL1, OWREGL1),
177 OP3(OACST, ORXREG1, OWREG1),
182 OP3(OACST, ORREGL1, OWREGL1),
187 OP3(ORREG1, ORXREG1, OWREG1),
192 OP3(OACST, ORXREG1, OWREG1),
198 OP3(ORREG1, ORREG1, OWREG1),
204 OP3(ORREG1, OACST, OWREG1)
[all...] |
| sparc.h | 291 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
300 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
301 #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
304 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
|
| h8300.h | 103 OP3 = 0x40000,
141 R3_8 = OP3 | L_8 | REG,
142 R3_16 = OP3 | L_16 | REG,
143 R3_32 = OP3 | L_32 | REG,
154 OP3PCREL8 = OP3 | PCREL | L_8,
155 OP3PCREL16 = OP3 | PCREL | L_16,
192 ABS8OP3 = OP3 | ABS | L_8,
193 ABS16OP3 = OP3 | ABS | L_16U,
194 ABS24OP3 = OP3 | ABS | L_24,
195 ABS32OP3 = OP3 | ABS | L_32
[all...] |
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| tic6x-opcode-table.h | 44 #define OP3(a, b, c) 3, { a, b, c }
162 OP3(ORREG1, ORXREG1, OWREG1),
167 OP3(ORREG1, ORXREG1, OWREGL1),
172 OP3(ORXREG1, ORREGL1, OWREGL1),
177 OP3(OACST, ORXREG1, OWREG1),
182 OP3(OACST, ORREGL1, OWREGL1),
187 OP3(ORREG1, ORXREG1, OWREG1),
192 OP3(OACST, ORXREG1, OWREG1),
198 OP3(ORREG1, ORREG1, OWREG1),
204 OP3(ORREG1, OACST, OWREG1)
[all...] |
| sparc.h | 291 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
300 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
301 #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
304 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
|
| h8300.h | 103 OP3 = 0x40000,
141 R3_8 = OP3 | L_8 | REG,
142 R3_16 = OP3 | L_16 | REG,
143 R3_32 = OP3 | L_32 | REG,
154 OP3PCREL8 = OP3 | PCREL | L_8,
155 OP3PCREL16 = OP3 | PCREL | L_16,
192 ABS8OP3 = OP3 | ABS | L_8,
193 ABS16OP3 = OP3 | ABS | L_16U,
194 ABS24OP3 = OP3 | ABS | L_24,
195 ABS32OP3 = OP3 | ABS | L_32
[all...] |
| /src/external/gpl3/gdb/dist/include/opcode/ |
| tic6x-opcode-table.h | 44 #define OP3(a, b, c) 3, { a, b, c }
162 OP3(ORREG1, ORXREG1, OWREG1),
167 OP3(ORREG1, ORXREG1, OWREGL1),
172 OP3(ORXREG1, ORREGL1, OWREGL1),
177 OP3(OACST, ORXREG1, OWREG1),
182 OP3(OACST, ORREGL1, OWREGL1),
187 OP3(ORREG1, ORXREG1, OWREG1),
192 OP3(OACST, ORXREG1, OWREG1),
198 OP3(ORREG1, ORREG1, OWREG1),
204 OP3(ORREG1, OACST, OWREG1)
[all...] |
| sparc.h | 291 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
300 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
301 #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
304 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
|
| h8300.h | 103 OP3 = 0x40000,
141 R3_8 = OP3 | L_8 | REG,
142 R3_16 = OP3 | L_16 | REG,
143 R3_32 = OP3 | L_32 | REG,
154 OP3PCREL8 = OP3 | PCREL | L_8,
155 OP3PCREL16 = OP3 | PCREL | L_16,
192 ABS8OP3 = OP3 | ABS | L_8,
193 ABS16OP3 = OP3 | ABS | L_16U,
194 ABS24OP3 = OP3 | ABS | L_24,
195 ABS32OP3 = OP3 | ABS | L_32
[all...] |
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| tic6x-opcode-table.h | 44 #define OP3(a, b, c) 3, { a, b, c }
162 OP3(ORREG1, ORXREG1, OWREG1),
167 OP3(ORREG1, ORXREG1, OWREGL1),
172 OP3(ORXREG1, ORREGL1, OWREGL1),
177 OP3(OACST, ORXREG1, OWREG1),
182 OP3(OACST, ORREGL1, OWREGL1),
187 OP3(ORREG1, ORXREG1, OWREG1),
192 OP3(OACST, ORXREG1, OWREG1),
198 OP3(ORREG1, ORREG1, OWREG1),
204 OP3(ORREG1, OACST, OWREG1)
[all...] |
| sparc.h | 291 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
300 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
301 #define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
304 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
|
| h8300.h | 103 OP3 = 0x40000,
141 R3_8 = OP3 | L_8 | REG,
142 R3_16 = OP3 | L_16 | REG,
143 R3_32 = OP3 | L_32 | REG,
154 OP3PCREL8 = OP3 | PCREL | L_8,
155 OP3PCREL16 = OP3 | PCREL | L_16,
192 ABS8OP3 = OP3 | ABS | L_8,
193 ABS16OP3 = OP3 | ABS | L_16U,
194 ABS24OP3 = OP3 | ABS | L_24,
195 ABS32OP3 = OP3 | ABS | L_32
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600Defines.h | 34 OP3 = (1 << 5),
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-rx.c | 2275 #define OP3(x) op[target_big_endian ? 2-x : x]
2325 OP3(0) = val & 0xff;
2326 OP3(1) = (val >> 8) & 0xff;
2327 OP3(2) = (val >> 16) & 0xff;
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-rx.c | 2275 #define OP3(x) op[target_big_endian ? 2-x : x]
2325 OP3(0) = val & 0xff;
2326 OP3(1) = (val >> 8) & 0xff;
2327 OP3(2) = (val >> 16) & 0xff;
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| aarch64-tbl.h | 34 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
2988 OP3 (MOPS_ADDR_Rd, MOPS_ADDR_Rs, MOPS_WB_Rn), QL_I3SAMEX, \
3015 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3043 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3044 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3045 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3047 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3050 CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF),
3051 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF),
3053 CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF)
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| aarch64-tbl.h | 34 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
3615 OP3 (MOPS_ADDR_Rd, MOPS_ADDR_Rs, MOPS_WB_Rn), QL_I3SAMEX, \
3642 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3691 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3692 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3693 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3695 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3698 CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
3699 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
3701 CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF)
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| aarch64-tbl.h | 34 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
3416 OP3 (MOPS_ADDR_Rd, MOPS_ADDR_Rs, MOPS_WB_Rn), QL_I3SAMEX, \
3443 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3471 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3472 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3473 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3475 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3478 CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
3479 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
3481 CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF)
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| aarch64-tbl.h | 34 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
3178 OP3 (MOPS_ADDR_Rd, MOPS_ADDR_Rs, MOPS_WB_Rn), QL_I3SAMEX, \
3205 OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
3233 CORE_INSN ("adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3234 CORE_INSN ("adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
3235 CORE_INSN ("sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3237 CORE_INSN ("sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF),
3240 CORE_INSN ("add", 0x0b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_SF),
3241 CORE_INSN ("adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_ADD | F_HAS_ALIAS | F_SF),
3243 CORE_INSN ("sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_ARITH_SUB | F_SF)
[all...] |
