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    Searched defs:Opcodes (Results 1 - 18 of 18) sorted by relevancy

  /src/external/gpl3/gdb/dist/sim/cr16/
gencode.c 113 long Opcodes[512];
124 if (Opcodes[i] == op)
125 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
  /src/external/gpl3/gdb.old/dist/sim/cr16/
gencode.c 113 long Opcodes[512];
124 if (Opcodes[i] == op)
125 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
  /src/external/gpl3/gdb/dist/sim/d10v/
gencode.c 85 long Opcodes[512];
94 if (Opcodes[i] == op)
95 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
120 Opcodes[curop++] = opcode->opcode;
  /src/external/gpl3/gdb.old/dist/sim/d10v/
gencode.c 85 long Opcodes[512];
94 if (Opcodes[i] == op)
95 fprintf(stderr,"DUPLICATE OPCODES: %lx\n", op);
120 Opcodes[curop++] = opcode->opcode;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrFMA3Info.h 10 // about existing X86 FMA3 opcodes, classifying and grouping them.
21 /// This class is used to group {132, 213, 231} forms of FMA opcodes together.
22 /// Each of the groups has either 3 opcodes, Also, each group has an attributes
25 /// An array holding 3 forms of FMA opcodes.
26 uint16_t Opcodes[3];
29 /// FMA groups of opcodes.
40 /// group of FMA opcodes consists of FMA intrinsic opcodes.
44 /// group of FMA opcodes consists of AVX512 opcodes accepting a k-mask an
    [all...]
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
SerialSnippetGenerator.cpp 42 std::vector<unsigned> Opcodes;
43 Opcodes.resize(State.getInstrInfo().getNumOpcodes());
44 std::iota(Opcodes.begin(), Opcodes.end(), 0U);
45 llvm::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
48 for (const unsigned OtherOpcode : Opcodes) {
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/
llvm-exegesis.cpp 53 cl::desc("opcode to measure, by index, or -1 to measure all opcodes"),
58 cl::desc("comma-separated list of opcodes to measure, by name"),
169 "default all such opcodes are filtered out. this flag will "
170 "instead show only such unstable opcodes"),
312 const auto Opcodes = getOpcodesOrDie(State.getInstrInfo());
332 if (!Opcodes.empty()) {
333 for (const unsigned Opcode : Opcodes) {
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
DAGISelMatcherOpt.cpp 393 StringSet<> Opcodes;
397 assert(Opcodes.insert(COM->getOpcode().getEnumName()).second &&
398 "Duplicate opcodes not factored?");
PredicateExpander.cpp 118 const RecVec &Opcodes) {
119 assert(!Opcodes.empty() && "Expected at least one opcode to check!");
122 if (Opcodes.size() == 1) {
124 expandCheckOpcode(OS, Opcodes[0]);
131 for (const Record *Rec : Opcodes) {
148 const RecVec &Opcodes) {
152 expandCheckOpcode(OS, Opcodes);
242 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes");
243 for (const Record *Opcode : Opcodes) {
    [all...]
CodeGenSchedule.h 355 std::vector<const Record *> Opcodes;
365 assert(!llvm::is_contained(Opcodes, Opcode) && "Opcode already in set!");
366 Opcodes.push_back(Opcode);
369 ArrayRef<const Record *> getOpcodes() const { return Opcodes; }
FixedLenDecoderEmitter.cpp 242 /// This recursive scheme ends when the number of Opcodes assigned to the
245 /// Opcodes assigned.
369 const std::vector<EncodingIDAndOpcode> &Opcodes;
398 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
409 : AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
563 for (unsigned i = 0, e = Owner->Opcodes.size(); i != e; ++i) {
567 Owner->insnWithID(Insn, Owner->Opcodes[i].EncodingID);
576 LastOpcFiltered = Owner->Opcodes[i];
582 VariableInstructions.push_back(Owner->Opcodes[i]);
1496 unsigned numInstructions = Opcodes.size()
    [all...]
CodeGenSchedule.cpp 119 // The generic opcodes are unsorted, handle them manually.
258 RecVec Opcodes = R->getValueAsListOfDefs("Opcodes");
259 if (Opcodes.empty()) {
295 // Number unique predicates and opcodes used by InstructionEquivalenceClass
305 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");
306 for (const Record *Opcode : Opcodes) {
316 // of which processors "use" which opcodes. We also want to be able to
337 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes")
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  /src/external/apache2/llvm/dist/llvm/include/llvm/Object/
MachO.h 161 /// rebasing opcodes. This allows you to iterate through the compressed table of
170 ArrayRef<uint8_t> opcodes, bool is64Bit);
192 ArrayRef<uint8_t> Opcodes;
205 /// binding opcodes. This allows you to iterate through the compressed table of
216 ArrayRef<uint8_t> Opcodes, bool is64Bit, MachOBindEntry::Kind);
244 ArrayRef<uint8_t> Opcodes;
392 /// For use examining rebase opcodes in a MachOObjectFile.
395 ArrayRef<uint8_t> Opcodes,
407 /// For use examining bind opcodes in a MachOObjectFile.
410 ArrayRef<uint8_t> Opcodes,
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 246 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);
248 if (!Opcodes.first)
251 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
  /src/external/apache2/llvm/dist/llvm/include/llvm/ObjectYAML/
DWARFYAML.h 152 std::vector<LineTableOpcode> Opcodes;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMInstructionSelector.cpp 84 // Store the opcodes that we might need, so we don't have to check what kind
128 } const Opcodes;
175 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),
347 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
350 return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
364 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
366 return isStore ? Opcodes.STORE16 : Opcodes.LOAD16
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ARMISelDAGToDAG.cpp 236 void SelectMVE_WB(SDNode *N, const uint16_t *Opcodes, bool Predicated);
256 /// opcodes for each element width.
274 /// pointer points to a set of NumVecs sub-opcodes used for the
277 const uint16_t *const *Opcodes, bool HasWriteback);
279 /// SelectMVE_VxDUP - Select MVE incrementing-dup instructions. Opcodes is an
281 void SelectMVE_VxDUP(SDNode *N, const uint16_t *Opcodes,
2530 void ARMDAGToDAGISel::SelectMVE_WB(SDNode *N, const uint16_t *Opcodes,
2538 Opcode = Opcodes[0];
2541 Opcode = Opcodes[1];
2692 const uint16_t *Opcodes = IsUnsigned ? OpcodesU : OpcodesS
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
AttributorAttributes.cpp 748 auto Opcodes = {
765 if (!A.checkForAllInstructions(CheckForNoUnwind, *this, Opcodes))
855 // The map from instruction opcodes to those instructions in the function.

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