| /src/external/gpl3/gcc/dist/libgcc/config/bfin/ |
| crtn.S | 37 P5 = [SP++];
46 P5 = [SP++];
|
| crti.S | 39 [--SP] = P5;
45 P5 = [P5 + _current_shared_library_p5_offset_]
52 [--SP] = P5;
58 P5 = [P5 + _current_shared_library_p5_offset_]
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/bfin/ |
| crtn.S | 37 P5 = [SP++];
46 P5 = [SP++];
|
| crti.S | 39 [--SP] = P5;
45 P5 = [P5 + _current_shared_library_p5_offset_]
52 [--SP] = P5;
58 P5 = [P5 + _current_shared_library_p5_offset_]
|
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| c_regmv_dr_pr.s | 21 P5 = R0;
26 CHECKREG p5, 0x20001001;
32 P5 = R1;
37 CHECKREG p5, 0x20021003;
43 P5 = R2;
48 CHECKREG p5, 0x20041005;
54 P5 = R3;
59 CHECKREG p5, 0x20061007;
65 P5 = R4;
70 CHECKREG p5, 0x20081009
[all...] |
| c_regmv_pr_pr.s | 12 imm32 p5, 0x200a100b;
18 imm32 p5, 0x200a100b;
23 P5 = P1;
28 CHECKREG p5, 0x20021003;
34 imm32 p5, 0x200a100b;
39 P5 = P2;
44 CHECKREG p5, 0x20041005;
50 imm32 p5, 0x200a100b;
55 P5 = P4;
60 CHECKREG p5, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 1 );
26 CHECKREG p5, 0x8E238057;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 1 );
48 CHECKREG p5, 0xF48C14CE;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 2 );
26 CHECKREG p5, 0x929BE2BF;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 2 );
48 CHECKREG p5, 0x929F8F70;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 2 )
[all...] |
| c_dsp32mac_pair_a0.s | 21 P5 = A0.w;
40 CHECKREG p5, 0xFF221DD6;
|
| c_ldimmhalf_lz_pr.s | 15 P5 = 0x000b (Z);
22 CHECKREG p5, 0x0000000b;
30 P5 = 0x00b0 (Z);
38 CHECKREG p5, 0x000000b0;
46 P5 = 0x0b00 (Z);
53 CHECKREG p5, 0x00000b00;
61 P5 = 0xb000 (Z);
68 CHECKREG p5, 0x0000b000;
|
| c_ldimmhalf_lzhi_pr.s | 21 P5 = 0x000b (Z);
22 P5.H = 0x000a;
31 CHECKREG p5, 0x000a000b;
43 P5 = 0x00b0 (Z);
44 P5.H = 0x00a0;
54 CHECKREG p5, 0x00a000b0;
66 P5 = 0x0b00 (Z);
67 P5.H = 0x0a00;
76 CHECKREG p5, 0x0a000b00;
88 P5 = 0xb000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 12 imm32 p5, 0x400a300b;
19 P5 = P1 >> 2;
26 CHECKREG p5, 0x30921203;
34 imm32 p5, 0xf00a900b;
41 P5 = P2;
48 CHECKREG p5, 0x26041005;
56 imm32 p5, 0x200a100b;
63 P5 = P3 << 2;
70 CHECKREG p5, 0x20061004;
78 imm32 p5, 0x260ae00b
[all...] |
| c_pushpopmultiple_preg.s | 17 P5 = 0xa5 (X);
18 [ -- SP ] = ( P5:1 );
23 P5 = 0;
24 ( P5:1 ) = [ SP ++ ];
29 CHECKREG p5, 0x000000a5;
34 P5 = 0xb5 (X);
35 [ -- SP ] = ( P5:2 );
39 P5 = 0;
40 ( P5:2 ) = [ SP ++ ];
45 CHECKREG p5, 0x000000b5
[all...] |
| stk5.s | 15 [ -- SP ] = ( R7:7, P5:4 );
20 ( R7:7, P5:4 ) = [ SP ++ ];
31 P5 = 8;
32 SP = SP + P5;
|
| c_compi2opp_pr_eq_i7_n.s | 13 P5 = -5;
21 CHECKREG p5, -5;
30 P5 = -13;
38 CHECKREG p5, -13;
47 P5 = -21;
55 CHECKREG p5, -21;
64 P5 = -29;
72 CHECKREG p5, -29;
81 P5 = -37;
89 CHECKREG p5, -37
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| c_regmv_dr_pr.s | 21 P5 = R0;
26 CHECKREG p5, 0x20001001;
32 P5 = R1;
37 CHECKREG p5, 0x20021003;
43 P5 = R2;
48 CHECKREG p5, 0x20041005;
54 P5 = R3;
59 CHECKREG p5, 0x20061007;
65 P5 = R4;
70 CHECKREG p5, 0x20081009
[all...] |
| c_regmv_pr_pr.s | 12 imm32 p5, 0x200a100b;
18 imm32 p5, 0x200a100b;
23 P5 = P1;
28 CHECKREG p5, 0x20021003;
34 imm32 p5, 0x200a100b;
39 P5 = P2;
44 CHECKREG p5, 0x20041005;
50 imm32 p5, 0x200a100b;
55 P5 = P4;
60 CHECKREG p5, 0x20081009
[all...] |
| c_comp3op_pr_plus_pr_sh1.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 1 );
26 CHECKREG p5, 0x8E238057;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 1 );
48 CHECKREG p5, 0xF48C14CE;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 1 )
[all...] |
| c_comp3op_pr_plus_pr_sh2.s | 12 imm32 p5, 0x78911345;
19 P5 = P1 + ( P5 << 2 );
26 CHECKREG p5, 0x929BE2BF;
34 imm32 p5, 0x78912325;
41 P5 = P2 + ( P5 << 2 );
48 CHECKREG p5, 0x929F8F70;
56 imm32 p5, 0x78912343;
63 P5 = P3 + ( P5 << 2 )
[all...] |
| c_dsp32mac_pair_a0.s | 21 P5 = A0.w;
40 CHECKREG p5, 0xFF221DD6;
|
| c_ldimmhalf_lz_pr.s | 15 P5 = 0x000b (Z);
22 CHECKREG p5, 0x0000000b;
30 P5 = 0x00b0 (Z);
38 CHECKREG p5, 0x000000b0;
46 P5 = 0x0b00 (Z);
53 CHECKREG p5, 0x00000b00;
61 P5 = 0xb000 (Z);
68 CHECKREG p5, 0x0000b000;
|
| c_ldimmhalf_lzhi_pr.s | 21 P5 = 0x000b (Z);
22 P5.H = 0x000a;
31 CHECKREG p5, 0x000a000b;
43 P5 = 0x00b0 (Z);
44 P5.H = 0x00a0;
54 CHECKREG p5, 0x00a000b0;
66 P5 = 0x0b00 (Z);
67 P5.H = 0x0a00;
76 CHECKREG p5, 0x0a000b00;
88 P5 = 0xb000 (Z)
[all...] |
| c_ptr2op_pr_sft_2_1.s | 12 imm32 p5, 0x400a300b;
19 P5 = P1 >> 2;
26 CHECKREG p5, 0x30921203;
34 imm32 p5, 0xf00a900b;
41 P5 = P2;
48 CHECKREG p5, 0x26041005;
56 imm32 p5, 0x200a100b;
63 P5 = P3 << 2;
70 CHECKREG p5, 0x20061004;
78 imm32 p5, 0x260ae00b
[all...] |
| c_pushpopmultiple_preg.s | 17 P5 = 0xa5 (X);
18 [ -- SP ] = ( P5:1 );
23 P5 = 0;
24 ( P5:1 ) = [ SP ++ ];
29 CHECKREG p5, 0x000000a5;
34 P5 = 0xb5 (X);
35 [ -- SP ] = ( P5:2 );
39 P5 = 0;
40 ( P5:2 ) = [ SP ++ ];
45 CHECKREG p5, 0x000000b5
[all...] |
| stk5.s | 15 [ -- SP ] = ( R7:7, P5:4 );
20 ( R7:7, P5:4 ) = [ SP ++ ];
31 P5 = 8;
32 SP = SP + P5;
|
