1 /* $NetBSD: qcom,gcc-ipq806x.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DT_BINDINGS_RESET_IPQ_806X_H 9 #define _DT_BINDINGS_RESET_IPQ_806X_H 10 11 #define QDSS_STM_RESET 0 12 #define AFAB_SMPSS_S_RESET 1 13 #define AFAB_SMPSS_M1_RESET 2 14 #define AFAB_SMPSS_M0_RESET 3 15 #define AFAB_EBI1_CH0_RESET 4 16 #define AFAB_EBI1_CH1_RESET 5 17 #define SFAB_ADM0_M0_RESET 6 18 #define SFAB_ADM0_M1_RESET 7 19 #define SFAB_ADM0_M2_RESET 8 20 #define ADM0_C2_RESET 9 21 #define ADM0_C1_RESET 10 22 #define ADM0_C0_RESET 11 23 #define ADM0_PBUS_RESET 12 24 #define ADM0_RESET 13 25 #define QDSS_CLKS_SW_RESET 14 26 #define QDSS_POR_RESET 15 27 #define QDSS_TSCTR_RESET 16 28 #define QDSS_HRESET_RESET 17 29 #define QDSS_AXI_RESET 18 30 #define QDSS_DBG_RESET 19 31 #define SFAB_PCIE_M_RESET 20 32 #define SFAB_PCIE_S_RESET 21 33 #define PCIE_EXT_RESET 22 34 #define PCIE_PHY_RESET 23 35 #define PCIE_PCI_RESET 24 36 #define PCIE_POR_RESET 25 37 #define PCIE_HCLK_RESET 26 38 #define PCIE_ACLK_RESET 27 39 #define SFAB_LPASS_RESET 28 40 #define SFAB_AFAB_M_RESET 29 41 #define AFAB_SFAB_M0_RESET 30 42 #define AFAB_SFAB_M1_RESET 31 43 #define SFAB_SATA_S_RESET 32 44 #define SFAB_DFAB_M_RESET 33 45 #define DFAB_SFAB_M_RESET 34 46 #define DFAB_SWAY0_RESET 35 47 #define DFAB_SWAY1_RESET 36 48 #define DFAB_ARB0_RESET 37 49 #define DFAB_ARB1_RESET 38 50 #define PPSS_PROC_RESET 39 51 #define PPSS_RESET 40 52 #define DMA_BAM_RESET 41 53 #define SPS_TIC_H_RESET 42 54 #define SFAB_CFPB_M_RESET 43 55 #define SFAB_CFPB_S_RESET 44 56 #define TSIF_H_RESET 45 57 #define CE1_H_RESET 46 58 #define CE1_CORE_RESET 47 59 #define CE1_SLEEP_RESET 48 60 #define CE2_H_RESET 49 61 #define CE2_CORE_RESET 50 62 #define SFAB_SFPB_M_RESET 51 63 #define SFAB_SFPB_S_RESET 52 64 #define RPM_PROC_RESET 53 65 #define PMIC_SSBI2_RESET 54 66 #define SDC1_RESET 55 67 #define SDC2_RESET 56 68 #define SDC3_RESET 57 69 #define SDC4_RESET 58 70 #define USB_HS1_RESET 59 71 #define USB_HSIC_RESET 60 72 #define USB_FS1_XCVR_RESET 61 73 #define USB_FS1_RESET 62 74 #define GSBI1_RESET 63 75 #define GSBI2_RESET 64 76 #define GSBI3_RESET 65 77 #define GSBI4_RESET 66 78 #define GSBI5_RESET 67 79 #define GSBI6_RESET 68 80 #define GSBI7_RESET 69 81 #define SPDM_RESET 70 82 #define SEC_CTRL_RESET 71 83 #define TLMM_H_RESET 72 84 #define SFAB_SATA_M_RESET 73 85 #define SATA_RESET 74 86 #define TSSC_RESET 75 87 #define PDM_RESET 76 88 #define MPM_H_RESET 77 89 #define MPM_RESET 78 90 #define SFAB_SMPSS_S_RESET 79 91 #define PRNG_RESET 80 92 #define SFAB_CE3_M_RESET 81 93 #define SFAB_CE3_S_RESET 82 94 #define CE3_SLEEP_RESET 83 95 #define PCIE_1_M_RESET 84 96 #define PCIE_1_S_RESET 85 97 #define PCIE_1_EXT_RESET 86 98 #define PCIE_1_PHY_RESET 87 99 #define PCIE_1_PCI_RESET 88 100 #define PCIE_1_POR_RESET 89 101 #define PCIE_1_HCLK_RESET 90 102 #define PCIE_1_ACLK_RESET 91 103 #define PCIE_2_M_RESET 92 104 #define PCIE_2_S_RESET 93 105 #define PCIE_2_EXT_RESET 94 106 #define PCIE_2_PHY_RESET 95 107 #define PCIE_2_PCI_RESET 96 108 #define PCIE_2_POR_RESET 97 109 #define PCIE_2_HCLK_RESET 98 110 #define PCIE_2_ACLK_RESET 99 111 #define SFAB_USB30_S_RESET 100 112 #define SFAB_USB30_M_RESET 101 113 #define USB30_0_PORT2_HS_PHY_RESET 102 114 #define USB30_0_MASTER_RESET 103 115 #define USB30_0_SLEEP_RESET 104 116 #define USB30_0_UTMI_PHY_RESET 105 117 #define USB30_0_POWERON_RESET 106 118 #define USB30_0_PHY_RESET 107 119 #define USB30_1_MASTER_RESET 108 120 #define USB30_1_SLEEP_RESET 109 121 #define USB30_1_UTMI_PHY_RESET 110 122 #define USB30_1_POWERON_RESET 111 123 #define USB30_1_PHY_RESET 112 124 #define NSSFB0_RESET 113 125 #define NSSFB1_RESET 114 126 #define UBI32_CORE1_CLKRST_CLAMP_RESET 115 127 #define UBI32_CORE1_CLAMP_RESET 116 128 #define UBI32_CORE1_AHB_RESET 117 129 #define UBI32_CORE1_AXI_RESET 118 130 #define UBI32_CORE2_CLKRST_CLAMP_RESET 119 131 #define UBI32_CORE2_CLAMP_RESET 120 132 #define UBI32_CORE2_AHB_RESET 121 133 #define UBI32_CORE2_AXI_RESET 122 134 #define GMAC_CORE1_RESET 123 135 #define GMAC_CORE2_RESET 124 136 #define GMAC_CORE3_RESET 125 137 #define GMAC_CORE4_RESET 126 138 #define GMAC_AHB_RESET 127 139 #define NSS_CH0_RST_RX_CLK_N_RESET 128 140 #define NSS_CH0_RST_TX_CLK_N_RESET 129 141 #define NSS_CH0_RST_RX_125M_N_RESET 130 142 #define NSS_CH0_HW_RST_RX_125M_N_RESET 131 143 #define NSS_CH0_RST_TX_125M_N_RESET 132 144 #define NSS_CH1_RST_RX_CLK_N_RESET 133 145 #define NSS_CH1_RST_TX_CLK_N_RESET 134 146 #define NSS_CH1_RST_RX_125M_N_RESET 135 147 #define NSS_CH1_HW_RST_RX_125M_N_RESET 136 148 #define NSS_CH1_RST_TX_125M_N_RESET 137 149 #define NSS_CH2_RST_RX_CLK_N_RESET 138 150 #define NSS_CH2_RST_TX_CLK_N_RESET 139 151 #define NSS_CH2_RST_RX_125M_N_RESET 140 152 #define NSS_CH2_HW_RST_RX_125M_N_RESET 141 153 #define NSS_CH2_RST_TX_125M_N_RESET 142 154 #define NSS_CH3_RST_RX_CLK_N_RESET 143 155 #define NSS_CH3_RST_TX_CLK_N_RESET 144 156 #define NSS_CH3_RST_RX_125M_N_RESET 145 157 #define NSS_CH3_HW_RST_RX_125M_N_RESET 146 158 #define NSS_CH3_RST_TX_125M_N_RESET 147 159 #define NSS_RST_RX_250M_125M_N_RESET 148 160 #define NSS_RST_TX_250M_125M_N_RESET 149 161 #define NSS_QSGMII_TXPI_RST_N_RESET 150 162 #define NSS_QSGMII_CDR_RST_N_RESET 151 163 #define NSS_SGMII2_CDR_RST_N_RESET 152 164 #define NSS_SGMII3_CDR_RST_N_RESET 153 165 #define NSS_CAL_PRBS_RST_N_RESET 154 166 #define NSS_LCKDT_RST_N_RESET 155 167 #define NSS_SRDS_N_RESET 156 168 169 #endif 170
Indexes created Tue Sep 30 20:09:53 GMT 2025