1 /* $NetBSD: if_pcn.c,v 1.81 2025/10/04 04:49:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.81 2025/10/04 04:49:20 thorpej Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/ioctl.h> 77 #include <sys/errno.h> 78 #include <sys/device.h> 79 #include <sys/queue.h> 80 81 #include <sys/rndsource.h> 82 83 #include <net/if.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_ether.h> 87 88 #include <net/bpf.h> 89 90 #include <sys/bus.h> 91 #include <sys/intr.h> 92 #include <machine/endian.h> 93 94 #include <dev/mii/mii.h> 95 #include <dev/mii/miivar.h> 96 97 #include <dev/ic/am79900reg.h> 98 #include <dev/ic/lancereg.h> 99 100 #include <dev/pci/pcireg.h> 101 #include <dev/pci/pcivar.h> 102 #include <dev/pci/pcidevs.h> 103 104 #include <dev/pci/if_pcnreg.h> 105 106 /* 107 * Transmit descriptor list size. This is arbitrary, but allocate 108 * enough descriptors for 128 pending transmissions, and 4 segments 109 * per packet. This MUST work out to a power of 2. 110 * 111 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 112 * 113 * So we play a little trick here. We give each packet up to 16 114 * DMA segments, but only allocate the max of 512 descriptors. The 115 * transmit logic can deal with this, we just are hoping to sneak by. 116 */ 117 #define PCN_NTXSEGS 16 118 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 119 120 #define PCN_TXQUEUELEN 128 121 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 122 #define PCN_NTXDESC 512 123 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 124 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 125 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 126 127 /* Tx interrupt every N + 1 packets. */ 128 #define PCN_TXINTR_MASK 7 129 130 /* 131 * Receive descriptor list size. We have one Rx buffer per incoming 132 * packet, so this logic is a little simpler. 133 */ 134 #define PCN_NRXDESC 128 135 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 136 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 137 138 /* 139 * Control structures are DMA'd to the PCnet chip. We allocate them in 140 * a single clump that maps to a single DMA segment to make several things 141 * easier. 142 */ 143 struct pcn_control_data { 144 /* The transmit descriptors. */ 145 struct letmd pcd_txdescs[PCN_NTXDESC]; 146 147 /* The receive descriptors. */ 148 struct lermd pcd_rxdescs[PCN_NRXDESC]; 149 150 /* The init block. */ 151 struct leinit pcd_initblock; 152 }; 153 154 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 155 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 156 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 157 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 158 159 /* 160 * Software state for transmit jobs. 161 */ 162 struct pcn_txsoft { 163 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 164 bus_dmamap_t txs_dmamap; /* our DMA map */ 165 int txs_firstdesc; /* first descriptor in packet */ 166 int txs_lastdesc; /* last descriptor in packet */ 167 }; 168 169 /* 170 * Software state for receive jobs. 171 */ 172 struct pcn_rxsoft { 173 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t rxs_dmamap; /* our DMA map */ 175 }; 176 177 /* 178 * Description of Rx FIFO watermarks for various revisions. 179 */ 180 static const char * const pcn_79c970_rcvfw[] = { 181 "16 bytes", 182 "64 bytes", 183 "128 bytes", 184 NULL, 185 }; 186 187 static const char * const pcn_79c971_rcvfw[] = { 188 "16 bytes", 189 "64 bytes", 190 "112 bytes", 191 NULL, 192 }; 193 194 /* 195 * Description of Tx start points for various revisions. 196 */ 197 static const char * const pcn_79c970_xmtsp[] = { 198 "8 bytes", 199 "64 bytes", 200 "128 bytes", 201 "248 bytes", 202 }; 203 204 static const char * const pcn_79c971_xmtsp[] = { 205 "20 bytes", 206 "64 bytes", 207 "128 bytes", 208 "248 bytes", 209 }; 210 211 static const char * const pcn_79c971_xmtsp_sram[] = { 212 "44 bytes", 213 "64 bytes", 214 "128 bytes", 215 "store-and-forward", 216 }; 217 218 /* 219 * Description of Tx FIFO watermarks for various revisions. 220 */ 221 static const char * const pcn_79c970_xmtfw[] = { 222 "16 bytes", 223 "64 bytes", 224 "128 bytes", 225 NULL, 226 }; 227 228 static const char * const pcn_79c971_xmtfw[] = { 229 "16 bytes", 230 "64 bytes", 231 "108 bytes", 232 NULL, 233 }; 234 235 /* 236 * Software state per device. 237 */ 238 struct pcn_softc { 239 device_t sc_dev; /* generic device information */ 240 bus_space_tag_t sc_st; /* bus space tag */ 241 bus_space_handle_t sc_sh; /* bus space handle */ 242 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 243 struct ethercom sc_ethercom; /* Ethernet common data */ 244 245 /* Points to our media routines, etc. */ 246 const struct pcn_variant *sc_variant; 247 248 void *sc_ih; /* interrupt cookie */ 249 250 struct mii_data sc_mii; /* MII/media information */ 251 252 callout_t sc_tick_ch; /* tick callout */ 253 254 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 255 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 256 257 /* Software state for transmit and receive descriptors. */ 258 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 259 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 260 261 /* Control data structures */ 262 struct pcn_control_data *sc_control_data; 263 #define sc_txdescs sc_control_data->pcd_txdescs 264 #define sc_rxdescs sc_control_data->pcd_rxdescs 265 #define sc_initblock sc_control_data->pcd_initblock 266 267 #ifdef PCN_EVENT_COUNTERS 268 /* Event counters. */ 269 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 270 struct evcnt sc_ev_txintr; /* Tx interrupts */ 271 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 272 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 273 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 274 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 275 276 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 277 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 278 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 279 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 280 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 281 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 282 struct evcnt sc_ev_txcopy; /* Tx copies required */ 283 #endif /* PCN_EVENT_COUNTERS */ 284 285 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 286 int sc_rcvfw; 287 288 const char * const *sc_xmtsp_desc; /* Tx start point info */ 289 int sc_xmtsp; 290 291 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 292 int sc_xmtfw; 293 294 int sc_flags; /* misc. flags; see below */ 295 int sc_swstyle; /* the software style in use */ 296 297 int sc_txfree; /* number of free Tx descriptors */ 298 int sc_txnext; /* next ready Tx descriptor */ 299 300 int sc_txsfree; /* number of free Tx jobs */ 301 int sc_txsnext; /* next free Tx job */ 302 int sc_txsdirty; /* dirty Tx jobs */ 303 304 int sc_rxptr; /* next ready Rx descriptor/job */ 305 306 uint32_t sc_csr5; /* prototype CSR5 register */ 307 uint32_t sc_mode; /* prototype MODE register */ 308 309 krndsource_t rnd_source; /* random source */ 310 }; 311 312 /* sc_flags */ 313 #define PCN_F_HAS_MII 0x0001 /* has MII */ 314 315 #ifdef PCN_EVENT_COUNTERS 316 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 317 #else 318 #define PCN_EVCNT_INCR(ev) /* nothing */ 319 #endif 320 321 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 322 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 323 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 324 325 #define PCN_CDTXSYNC(sc, x, n, ops) \ 326 do { \ 327 int __x, __n; \ 328 \ 329 __x = (x); \ 330 __n = (n); \ 331 \ 332 /* If it will wrap around, sync to the end of the ring. */ \ 333 if ((__x + __n) > PCN_NTXDESC) { \ 334 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 335 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 336 (PCN_NTXDESC - __x), (ops)); \ 337 __n -= (PCN_NTXDESC - __x); \ 338 __x = 0; \ 339 } \ 340 \ 341 /* Now sync whatever is left. */ \ 342 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 343 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 344 } while (/*CONSTCOND*/0) 345 346 #define PCN_CDRXSYNC(sc, x, ops) \ 347 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 348 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 349 350 #define PCN_CDINITSYNC(sc, ops) \ 351 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 352 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 353 354 #define PCN_INIT_RXDESC(sc, x) \ 355 do { \ 356 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 357 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 358 struct mbuf *__m = __rxs->rxs_mbuf; \ 359 \ 360 /* \ 361 * Note: We scoot the packet forward 2 bytes in the buffer \ 362 * so that the payload after the Ethernet header is aligned \ 363 * to a 4-byte boundary. \ 364 */ \ 365 __m->m_data = __m->m_ext.ext_buf + 2; \ 366 \ 367 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 368 __rmd->rmd2 = \ 369 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 370 __rmd->rmd0 = 0; \ 371 } else { \ 372 __rmd->rmd2 = 0; \ 373 __rmd->rmd0 = \ 374 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 375 } \ 376 __rmd->rmd1 = htole32(LE_R1_OWN | LE_R1_ONES | \ 377 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 378 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);\ 379 } while(/*CONSTCOND*/0) 380 381 static void pcn_start(struct ifnet *); 382 static void pcn_watchdog(struct ifnet *); 383 static int pcn_ioctl(struct ifnet *, u_long, void *); 384 static int pcn_init(struct ifnet *); 385 static void pcn_stop(struct ifnet *, int); 386 387 static bool pcn_shutdown(device_t, int); 388 389 static void pcn_reset(struct pcn_softc *); 390 static void pcn_rxdrain(struct pcn_softc *); 391 static int pcn_add_rxbuf(struct pcn_softc *, int); 392 static void pcn_tick(void *); 393 394 static void pcn_spnd(struct pcn_softc *); 395 396 static void pcn_set_filter(struct pcn_softc *); 397 398 static int pcn_intr(void *); 399 static void pcn_txintr(struct pcn_softc *); 400 static int pcn_rxintr(struct pcn_softc *); 401 402 static int pcn_mii_readreg(device_t, int, int, uint16_t *); 403 static int pcn_mii_writereg(device_t, int, int, uint16_t); 404 static void pcn_mii_statchg(struct ifnet *); 405 406 static void pcn_79c970_mediainit(struct pcn_softc *); 407 static int pcn_79c970_mediachange(struct ifnet *); 408 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 409 410 static void pcn_79c971_mediainit(struct pcn_softc *); 411 412 /* 413 * Description of a PCnet-PCI variant. Used to select media access 414 * method, mostly, and to print a nice description of the chip. 415 */ 416 static const struct pcn_variant { 417 const char *pcv_desc; 418 void (*pcv_mediainit)(struct pcn_softc *); 419 uint16_t pcv_chipid; 420 } pcn_variants[] = { 421 { "Am79c970 PCnet-PCI", 422 pcn_79c970_mediainit, 423 PARTID_Am79c970 }, 424 425 { "Am79c970A PCnet-PCI II", 426 pcn_79c970_mediainit, 427 PARTID_Am79c970A }, 428 429 { "Am79c971 PCnet-FAST", 430 pcn_79c971_mediainit, 431 PARTID_Am79c971 }, 432 433 { "Am79c972 PCnet-FAST+", 434 pcn_79c971_mediainit, 435 PARTID_Am79c972 }, 436 437 { "Am79c973 PCnet-FAST III", 438 pcn_79c971_mediainit, 439 PARTID_Am79c973 }, 440 441 { "Am79c975 PCnet-FAST III", 442 pcn_79c971_mediainit, 443 PARTID_Am79c975 }, 444 445 { "Unknown PCnet-PCI variant", 446 pcn_79c971_mediainit, 447 0 }, 448 }; 449 450 int pcn_copy_small = 0; 451 452 static int pcn_match(device_t, cfdata_t, void *); 453 static void pcn_attach(device_t, device_t, void *); 454 455 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 456 pcn_match, pcn_attach, NULL, NULL); 457 458 /* 459 * Routines to read and write the PCnet-PCI CSR/BCR space. 460 */ 461 462 static inline uint32_t 463 pcn_csr_read(struct pcn_softc *sc, int reg) 464 { 465 466 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 467 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP); 468 } 469 470 static inline void 471 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 472 { 473 474 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 475 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 476 } 477 478 static inline uint32_t 479 pcn_bcr_read(struct pcn_softc *sc, int reg) 480 { 481 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 483 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP); 484 } 485 486 static inline void 487 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 488 { 489 490 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 491 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 492 } 493 494 static bool 495 pcn_is_vmware(const char *enaddr) 496 { 497 498 /* 499 * VMware uses the OUI 00:0c:29 for auto-generated MAC 500 * addresses. 501 */ 502 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 503 return TRUE; 504 505 /* 506 * VMware uses the OUI 00:50:56 for manually-set MAC 507 * addresses (and some auto-generated ones). 508 */ 509 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 510 return TRUE; 511 512 return FALSE; 513 } 514 515 static const struct pcn_variant * 516 pcn_lookup_variant(uint16_t chipid) 517 { 518 const struct pcn_variant *pcv; 519 520 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 521 if (chipid == pcv->pcv_chipid) 522 return pcv; 523 } 524 525 /* 526 * This covers unknown chips, which we simply treat like 527 * a generic PCnet-FAST. 528 */ 529 return pcv; 530 } 531 532 static int 533 pcn_match(device_t parent, cfdata_t cf, void *aux) 534 { 535 struct pci_attach_args *pa = aux; 536 537 /* 538 * IBM Makes a PCI variant of this card which shows up as a 539 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 540 * this card is truly a pcn card, so we have a special case match for 541 * it 542 */ 543 544 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 545 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 546 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 547 return 1; 548 549 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 550 return 0; 551 552 switch (PCI_PRODUCT(pa->pa_id)) { 553 case PCI_PRODUCT_AMD_PCNET_PCI: 554 /* Beat if_le_pci.c */ 555 return 10; 556 } 557 558 return 0; 559 } 560 561 static void 562 pcn_attach(device_t parent, device_t self, void *aux) 563 { 564 struct pcn_softc *sc = device_private(self); 565 struct pci_attach_args *pa = aux; 566 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 567 pci_chipset_tag_t pc = pa->pa_pc; 568 pci_intr_handle_t ih; 569 const char *intrstr = NULL; 570 bus_space_tag_t iot, memt; 571 bus_space_handle_t ioh, memh; 572 bus_dma_segment_t seg; 573 int ioh_valid, memh_valid; 574 int ntxsegs, i, rseg, error; 575 uint32_t chipid, reg; 576 uint8_t enaddr[ETHER_ADDR_LEN]; 577 bool is_vmware; 578 char intrbuf[PCI_INTRSTR_LEN]; 579 580 sc->sc_dev = self; 581 callout_init(&sc->sc_tick_ch, 0); 582 callout_setfunc(&sc->sc_tick_ch, pcn_tick, sc); 583 584 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 585 586 /* 587 * Map the device. 588 */ 589 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 590 &iot, &ioh, NULL, NULL) == 0); 591 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 592 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 593 &memt, &memh, NULL, NULL) == 0); 594 595 if (memh_valid) { 596 sc->sc_st = memt; 597 sc->sc_sh = memh; 598 } else if (ioh_valid) { 599 sc->sc_st = iot; 600 sc->sc_sh = ioh; 601 } else { 602 aprint_error_dev(self, "unable to map device registers\n"); 603 return; 604 } 605 606 sc->sc_dmat = pa->pa_dmat; 607 608 /* Make sure bus mastering is enabled. */ 609 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 610 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 611 PCI_COMMAND_MASTER_ENABLE); 612 613 /* power up chip */ 614 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 615 NULL)) && error != EOPNOTSUPP) { 616 aprint_error_dev(self, "cannot activate %d\n", error); 617 return; 618 } 619 620 /* 621 * Reset the chip to a known state. This also puts the 622 * chip into 32-bit mode. 623 */ 624 pcn_reset(sc); 625 626 /* 627 * On some systems with the chip is an on-board device, the 628 * EEPROM is not used. Handle this by reading the MAC address 629 * from the CSRs (assuming that boot firmware has written 630 * it there). 631 */ 632 if (device_getprop_bool(sc->sc_dev, "am79c970-no-eeprom")) { 633 for (i = 0; i < 3; i++) { 634 uint32_t val; 635 val = pcn_csr_read(sc, LE_CSR12 + i); 636 enaddr[2 * i] = val & 0xff; 637 enaddr[2 * i + 1] = (val >> 8) & 0xff; 638 } 639 } else { 640 for (i = 0; i < ETHER_ADDR_LEN; i++) { 641 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 642 PCN32_APROM + i); 643 } 644 } 645 646 /* Check to see if this is a VMware emulated network interface. */ 647 is_vmware = pcn_is_vmware(enaddr); 648 649 /* 650 * Now that the device is mapped, attempt to figure out what 651 * kind of chip we have. Note that IDL has all 32 bits of 652 * the chip ID when we're in 32-bit mode. 653 */ 654 chipid = pcn_csr_read(sc, LE_CSR88); 655 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 656 657 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 658 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 659 ether_sprintf(enaddr)); 660 661 /* 662 * VMware has a bug in its network interface emulation; we must 663 * limit the number of Tx segments. 664 */ 665 if (is_vmware) { 666 device_setprop_bool(sc->sc_dev, "am79c970-vmware-tx-bug", true); 667 ntxsegs = PCN_NTXSEGS_VMWARE; 668 aprint_verbose_dev(self, 669 "VMware Tx segment count bug detected\n"); 670 } else { 671 ntxsegs = PCN_NTXSEGS; 672 } 673 674 /* 675 * Map and establish our interrupt. 676 */ 677 if (pci_intr_map(pa, &ih)) { 678 aprint_error_dev(self, "unable to map interrupt\n"); 679 return; 680 } 681 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 682 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, pcn_intr, sc, 683 device_xname(self)); 684 if (sc->sc_ih == NULL) { 685 aprint_error_dev(self, "unable to establish interrupt"); 686 if (intrstr != NULL) 687 aprint_error(" at %s", intrstr); 688 aprint_error("\n"); 689 return; 690 } 691 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 692 693 /* 694 * Allocate the control data structures, and create and load the 695 * DMA map for it. 696 */ 697 if ((error = bus_dmamem_alloc(sc->sc_dmat, 698 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 699 0)) != 0) { 700 aprint_error_dev(self, "unable to allocate control data, " 701 "error = %d\n", error); 702 goto fail_0; 703 } 704 705 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 706 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 707 BUS_DMA_COHERENT)) != 0) { 708 aprint_error_dev(self, "unable to map control data, " 709 "error = %d\n", error); 710 goto fail_1; 711 } 712 713 if ((error = bus_dmamap_create(sc->sc_dmat, 714 sizeof(struct pcn_control_data), 1, 715 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 716 aprint_error_dev(self, "unable to create control data DMA map, " 717 "error = %d\n", error); 718 goto fail_2; 719 } 720 721 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 722 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 723 0)) != 0) { 724 aprint_error_dev(self, 725 "unable to load control data DMA map, error = %d\n", error); 726 goto fail_3; 727 } 728 729 /* Create the transmit buffer DMA maps. */ 730 for (i = 0; i < PCN_TXQUEUELEN; i++) { 731 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 732 ntxsegs, MCLBYTES, 0, 0, 733 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 734 aprint_error_dev(self, 735 "unable to create tx DMA map %d, error = %d\n", 736 i, error); 737 goto fail_4; 738 } 739 } 740 741 /* Create the receive buffer DMA maps. */ 742 for (i = 0; i < PCN_NRXDESC; i++) { 743 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 744 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 745 aprint_error_dev(self, 746 "unable to create rx DMA map %d, error = %d\n", 747 i, error); 748 goto fail_5; 749 } 750 sc->sc_rxsoft[i].rxs_mbuf = NULL; 751 } 752 753 /* Initialize our media structures. */ 754 (*sc->sc_variant->pcv_mediainit)(sc); 755 756 /* 757 * Initialize FIFO watermark info. 758 */ 759 switch (sc->sc_variant->pcv_chipid) { 760 case PARTID_Am79c970: 761 case PARTID_Am79c970A: 762 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 763 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 764 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 765 break; 766 767 default: 768 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 769 /* 770 * Read BCR25 to determine how much SRAM is 771 * on the board. If > 0, then we the chip 772 * uses different Start Point thresholds. 773 * 774 * Note BCR25 and BCR26 are loaded from the 775 * EEPROM on RST, and unaffected by S_RESET, 776 * so we don't really have to worry about 777 * them except for this. 778 */ 779 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 780 if (reg != 0) 781 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 782 else 783 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 784 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 785 break; 786 } 787 788 /* 789 * Set up defaults -- see the tables above for what these 790 * values mean. 791 * 792 * XXX How should we tune RCVFW and XMTFW? 793 */ 794 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 795 sc->sc_xmtsp = 1; 796 sc->sc_xmtfw = 0; 797 798 ifp = &sc->sc_ethercom.ec_if; 799 strcpy(ifp->if_xname, device_xname(self)); 800 ifp->if_softc = sc; 801 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 802 ifp->if_ioctl = pcn_ioctl; 803 ifp->if_start = pcn_start; 804 ifp->if_watchdog = pcn_watchdog; 805 ifp->if_init = pcn_init; 806 ifp->if_stop = pcn_stop; 807 IFQ_SET_READY(&ifp->if_snd); 808 809 /* Attach the interface. */ 810 if_attach(ifp); 811 if_deferred_start_init(ifp, NULL); 812 ether_ifattach(ifp, enaddr); 813 rnd_attach_source(&sc->rnd_source, device_xname(self), 814 RND_TYPE_NET, RND_FLAG_DEFAULT); 815 816 #ifdef PCN_EVENT_COUNTERS 817 /* Attach event counters. */ 818 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 819 NULL, device_xname(self), "txdstall"); 820 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 821 NULL, device_xname(self), "txintr"); 822 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 823 NULL, device_xname(self), "rxintr"); 824 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 825 NULL, device_xname(self), "babl"); 826 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 827 NULL, device_xname(self), "miss"); 828 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 829 NULL, device_xname(self), "merr"); 830 831 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 832 NULL, device_xname(self), "txseg1"); 833 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 834 NULL, device_xname(self), "txseg2"); 835 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 836 NULL, device_xname(self), "txseg3"); 837 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 838 NULL, device_xname(self), "txseg4"); 839 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 840 NULL, device_xname(self), "txseg5"); 841 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 842 NULL, device_xname(self), "txsegmore"); 843 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 844 NULL, device_xname(self), "txcopy"); 845 #endif /* PCN_EVENT_COUNTERS */ 846 847 /* 848 * Establish power handler with shutdown hook, to make sure 849 * the interface is shutdown during reboot. 850 */ 851 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 852 pmf_class_network_register(self, ifp); 853 else 854 aprint_error_dev(self, "couldn't establish power handler\n"); 855 856 return; 857 858 /* 859 * Free any resources we've allocated during the failed attach 860 * attempt. Do this in reverse order and fall through. 861 */ 862 fail_5: 863 for (i = 0; i < PCN_NRXDESC; i++) { 864 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 865 bus_dmamap_destroy(sc->sc_dmat, 866 sc->sc_rxsoft[i].rxs_dmamap); 867 } 868 fail_4: 869 for (i = 0; i < PCN_TXQUEUELEN; i++) { 870 if (sc->sc_txsoft[i].txs_dmamap != NULL) 871 bus_dmamap_destroy(sc->sc_dmat, 872 sc->sc_txsoft[i].txs_dmamap); 873 } 874 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 875 fail_3: 876 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 877 fail_2: 878 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 879 sizeof(struct pcn_control_data)); 880 fail_1: 881 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 882 fail_0: 883 return; 884 } 885 886 /* 887 * pcn_shutdown: 888 * 889 * Make sure the interface is stopped at reboot time. 890 */ 891 static bool 892 pcn_shutdown(device_t self, int howto) 893 { 894 struct pcn_softc *sc = device_private(self); 895 896 pcn_stop(&sc->sc_ethercom.ec_if, 1); 897 /* explicitly reset the chip for some onboard one with lazy firmware */ 898 pcn_reset(sc); 899 900 return true; 901 } 902 903 /* 904 * pcn_start: [ifnet interface function] 905 * 906 * Start packet transmission on the interface. 907 */ 908 static void 909 pcn_start(struct ifnet *ifp) 910 { 911 struct pcn_softc *sc = ifp->if_softc; 912 struct mbuf *m0, *m; 913 struct pcn_txsoft *txs; 914 bus_dmamap_t dmamap; 915 int error, nexttx, lasttx = -1, ofree, seg; 916 917 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 918 return; 919 920 /* 921 * Remember the previous number of free descriptors and 922 * the first descriptor we'll use. 923 */ 924 ofree = sc->sc_txfree; 925 926 /* 927 * Loop through the send queue, setting up transmit descriptors 928 * until we drain the queue, or use up all available transmit 929 * descriptors. 930 */ 931 while (sc->sc_txsfree != 0) { 932 /* Grab a packet off the queue. */ 933 IFQ_POLL(&ifp->if_snd, m0); 934 if (m0 == NULL) 935 break; 936 m = NULL; 937 938 txs = &sc->sc_txsoft[sc->sc_txsnext]; 939 dmamap = txs->txs_dmamap; 940 941 /* 942 * Load the DMA map. If this fails, the packet either 943 * didn't fit in the allotted number of segments, or we 944 * were short on resources. In this case, we'll copy 945 * and try again. 946 */ 947 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 948 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 949 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 950 MGETHDR(m, M_DONTWAIT, MT_DATA); 951 if (m == NULL) { 952 printf("%s: unable to allocate Tx mbuf\n", 953 device_xname(sc->sc_dev)); 954 break; 955 } 956 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 957 if (m0->m_pkthdr.len > MHLEN) { 958 MCLGET(m, M_DONTWAIT); 959 if ((m->m_flags & M_EXT) == 0) { 960 printf("%s: unable to allocate Tx " 961 "cluster\n", 962 device_xname(sc->sc_dev)); 963 m_freem(m); 964 break; 965 } 966 } 967 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 968 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 969 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 970 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 971 if (error) { 972 printf("%s: unable to load Tx buffer, " 973 "error = %d\n", device_xname(sc->sc_dev), 974 error); 975 m_freem(m); 976 break; 977 } 978 } 979 980 /* 981 * Ensure we have enough descriptors free to describe 982 * the packet. Note, we always reserve one descriptor 983 * at the end of the ring as a termination point, to 984 * prevent wrap-around. 985 */ 986 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 987 /* 988 * Not enough free descriptors to transmit this 989 * packet. 990 */ 991 bus_dmamap_unload(sc->sc_dmat, dmamap); 992 m_freem(m); 993 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 994 break; 995 } 996 997 IFQ_DEQUEUE(&ifp->if_snd, m0); 998 if (m != NULL) { 999 m_freem(m0); 1000 m0 = m; 1001 } 1002 1003 /* 1004 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1005 */ 1006 1007 /* Sync the DMA map. */ 1008 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1009 BUS_DMASYNC_PREWRITE); 1010 1011 #ifdef PCN_EVENT_COUNTERS 1012 switch (dmamap->dm_nsegs) { 1013 case 1: 1014 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1015 break; 1016 case 2: 1017 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1018 break; 1019 case 3: 1020 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1021 break; 1022 case 4: 1023 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1024 break; 1025 case 5: 1026 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1027 break; 1028 default: 1029 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1030 break; 1031 } 1032 #endif /* PCN_EVENT_COUNTERS */ 1033 1034 /* 1035 * Initialize the transmit descriptors. 1036 */ 1037 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1038 for (nexttx = sc->sc_txnext, seg = 0; 1039 seg < dmamap->dm_nsegs; 1040 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1041 /* 1042 * If this is the first descriptor we're 1043 * enqueueing, don't set the OWN bit just 1044 * yet. That could cause a race condition. 1045 * We'll do it below. 1046 */ 1047 sc->sc_txdescs[nexttx].tmd0 = 0; 1048 sc->sc_txdescs[nexttx].tmd2 = 1049 htole32(dmamap->dm_segs[seg].ds_addr); 1050 sc->sc_txdescs[nexttx].tmd1 = 1051 htole32(LE_T1_ONES | 1052 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1053 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1054 LE_T1_BCNT_MASK)); 1055 lasttx = nexttx; 1056 } 1057 } else { 1058 for (nexttx = sc->sc_txnext, seg = 0; 1059 seg < dmamap->dm_nsegs; 1060 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1061 /* 1062 * If this is the first descriptor we're 1063 * enqueueing, don't set the OWN bit just 1064 * yet. That could cause a race condition. 1065 * We'll do it below. 1066 */ 1067 sc->sc_txdescs[nexttx].tmd0 = 1068 htole32(dmamap->dm_segs[seg].ds_addr); 1069 sc->sc_txdescs[nexttx].tmd2 = 0; 1070 sc->sc_txdescs[nexttx].tmd1 = 1071 htole32(LE_T1_ONES | 1072 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1073 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1074 LE_T1_BCNT_MASK)); 1075 lasttx = nexttx; 1076 } 1077 } 1078 1079 KASSERT(lasttx != -1); 1080 /* Interrupt on the packet, if appropriate. */ 1081 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1082 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1083 1084 /* Set `start of packet' and `end of packet' appropriately. */ 1085 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1086 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1087 htole32(LE_T1_OWN | LE_T1_STP); 1088 1089 /* Sync the descriptors we're using. */ 1090 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1092 1093 /* Kick the transmitter. */ 1094 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD); 1095 1096 /* 1097 * Store a pointer to the packet so we can free it later, 1098 * and remember what txdirty will be once the packet is 1099 * done. 1100 */ 1101 txs->txs_mbuf = m0; 1102 txs->txs_firstdesc = sc->sc_txnext; 1103 txs->txs_lastdesc = lasttx; 1104 1105 /* Advance the tx pointer. */ 1106 sc->sc_txfree -= dmamap->dm_nsegs; 1107 sc->sc_txnext = nexttx; 1108 1109 sc->sc_txsfree--; 1110 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1111 1112 /* Pass the packet to any BPF listeners. */ 1113 bpf_mtap(ifp, m0, BPF_D_OUT); 1114 } 1115 1116 if (sc->sc_txfree != ofree) { 1117 /* Set a watchdog timer in case the chip flakes out. */ 1118 ifp->if_timer = 5; 1119 } 1120 } 1121 1122 /* 1123 * pcn_watchdog: [ifnet interface function] 1124 * 1125 * Watchdog timer handler. 1126 */ 1127 static void 1128 pcn_watchdog(struct ifnet *ifp) 1129 { 1130 struct pcn_softc *sc = ifp->if_softc; 1131 1132 /* 1133 * Since we're not interrupting every packet, sweep 1134 * up before we report an error. 1135 */ 1136 pcn_txintr(sc); 1137 1138 if (sc->sc_txfree != PCN_NTXDESC) { 1139 printf("%s: device timeout (txfree %d txsfree %d)\n", 1140 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1141 if_statinc(ifp, if_oerrors); 1142 1143 /* Reset the interface. */ 1144 (void) pcn_init(ifp); 1145 } 1146 1147 /* Try to get more packets going. */ 1148 pcn_start(ifp); 1149 } 1150 1151 /* 1152 * pcn_ioctl: [ifnet interface function] 1153 * 1154 * Handle control requests from the operator. 1155 */ 1156 static int 1157 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1158 { 1159 int s, error; 1160 1161 s = splnet(); 1162 1163 switch (cmd) { 1164 default: 1165 error = ether_ioctl(ifp, cmd, data); 1166 if (error == ENETRESET) { 1167 /* 1168 * Multicast list has changed; set the hardware filter 1169 * accordingly. 1170 */ 1171 if (ifp->if_flags & IFF_RUNNING) 1172 error = pcn_init(ifp); 1173 else 1174 error = 0; 1175 } 1176 break; 1177 } 1178 1179 /* Try to get more packets going. */ 1180 pcn_start(ifp); 1181 1182 splx(s); 1183 return error; 1184 } 1185 1186 /* 1187 * pcn_intr: 1188 * 1189 * Interrupt service routine. 1190 */ 1191 static int 1192 pcn_intr(void *arg) 1193 { 1194 struct pcn_softc *sc = arg; 1195 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1196 uint32_t csr0; 1197 int wantinit, handled = 0; 1198 1199 for (wantinit = 0; wantinit == 0;) { 1200 csr0 = pcn_csr_read(sc, LE_CSR0); 1201 if ((csr0 & LE_C0_INTR) == 0) 1202 break; 1203 1204 rnd_add_uint32(&sc->rnd_source, csr0); 1205 1206 /* ACK the bits and re-enable interrupts. */ 1207 pcn_csr_write(sc, LE_CSR0, csr0 & 1208 (LE_C0_INEA | LE_C0_BABL | LE_C0_MISS | LE_C0_MERR | 1209 LE_C0_RINT | LE_C0_TINT | LE_C0_IDON)); 1210 1211 handled = 1; 1212 1213 if (csr0 & LE_C0_RINT) { 1214 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1215 wantinit = pcn_rxintr(sc); 1216 } 1217 1218 if (csr0 & LE_C0_TINT) { 1219 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1220 pcn_txintr(sc); 1221 } 1222 1223 if (csr0 & LE_C0_ERR) { 1224 if (csr0 & LE_C0_BABL) { 1225 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1226 if_statinc(ifp, if_oerrors); 1227 } 1228 if (csr0 & LE_C0_MISS) { 1229 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1230 if_statinc(ifp, if_ierrors); 1231 } 1232 if (csr0 & LE_C0_MERR) { 1233 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1234 printf("%s: memory error\n", 1235 device_xname(sc->sc_dev)); 1236 wantinit = 1; 1237 break; 1238 } 1239 } 1240 1241 if ((csr0 & LE_C0_RXON) == 0) { 1242 printf("%s: receiver disabled\n", 1243 device_xname(sc->sc_dev)); 1244 if_statinc(ifp, if_ierrors); 1245 wantinit = 1; 1246 } 1247 1248 if ((csr0 & LE_C0_TXON) == 0) { 1249 printf("%s: transmitter disabled\n", 1250 device_xname(sc->sc_dev)); 1251 if_statinc(ifp, if_oerrors); 1252 wantinit = 1; 1253 } 1254 } 1255 1256 if (handled) { 1257 if (wantinit) 1258 pcn_init(ifp); 1259 1260 /* Try to get more packets going. */ 1261 if_schedule_deferred_start(ifp); 1262 } 1263 1264 return handled; 1265 } 1266 1267 /* 1268 * pcn_spnd: 1269 * 1270 * Suspend the chip. 1271 */ 1272 static void 1273 pcn_spnd(struct pcn_softc *sc) 1274 { 1275 int i; 1276 1277 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1278 1279 for (i = 0; i < 10000; i++) { 1280 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1281 return; 1282 delay(5); 1283 } 1284 1285 printf("%s: WARNING: chip failed to enter suspended state\n", 1286 device_xname(sc->sc_dev)); 1287 } 1288 1289 /* 1290 * pcn_txintr: 1291 * 1292 * Helper; handle transmit interrupts. 1293 */ 1294 static void 1295 pcn_txintr(struct pcn_softc *sc) 1296 { 1297 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1298 struct pcn_txsoft *txs; 1299 uint32_t tmd1, tmd2, tmd; 1300 int i, j; 1301 1302 /* 1303 * Go through our Tx list and free mbufs for those 1304 * frames which have been transmitted. 1305 */ 1306 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1307 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1308 txs = &sc->sc_txsoft[i]; 1309 1310 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1311 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1312 1313 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1314 if (tmd1 & LE_T1_OWN) 1315 break; 1316 1317 /* 1318 * Slightly annoying -- we have to loop through the 1319 * descriptors we've used looking for ERR, since it 1320 * can appear on any descriptor in the chain. 1321 */ 1322 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1323 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1324 if (tmd & LE_T1_ERR) { 1325 if_statinc(ifp, if_oerrors); 1326 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1327 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1328 else 1329 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1330 if (tmd2 & LE_T2_UFLO) { 1331 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1332 sc->sc_xmtsp++; 1333 printf("%s: transmit " 1334 "underrun; new threshold: " 1335 "%s\n", 1336 device_xname(sc->sc_dev), 1337 sc->sc_xmtsp_desc[ 1338 sc->sc_xmtsp]); 1339 pcn_spnd(sc); 1340 pcn_csr_write(sc, LE_CSR80, 1341 LE_C80_RCVFW(sc->sc_rcvfw) | 1342 LE_C80_XMTSP(sc->sc_xmtsp) | 1343 LE_C80_XMTFW(sc->sc_xmtfw)); 1344 pcn_csr_write(sc, LE_CSR5, 1345 sc->sc_csr5); 1346 } else { 1347 printf("%s: transmit " 1348 "underrun\n", 1349 device_xname(sc->sc_dev)); 1350 } 1351 } else if (tmd2 & LE_T2_BUFF) { 1352 printf("%s: transmit buffer error\n", 1353 device_xname(sc->sc_dev)); 1354 } 1355 if (tmd2 & LE_T2_LCOL) 1356 if_statinc(ifp, if_collisions); 1357 if (tmd2 & LE_T2_RTRY) 1358 if_statadd(ifp, if_collisions, 16); 1359 goto next_packet; 1360 } 1361 if (j == txs->txs_lastdesc) 1362 break; 1363 } 1364 if (tmd1 & LE_T1_ONE) 1365 if_statinc(ifp, if_collisions); 1366 else if (tmd & LE_T1_MORE) { 1367 /* Real number is unknown. */ 1368 if_statadd(ifp, if_collisions, 2); 1369 } 1370 if_statinc(ifp, if_opackets); 1371 next_packet: 1372 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1373 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1374 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1375 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1376 m_freem(txs->txs_mbuf); 1377 txs->txs_mbuf = NULL; 1378 } 1379 1380 /* Update the dirty transmit buffer pointer. */ 1381 sc->sc_txsdirty = i; 1382 1383 /* 1384 * If there are no more pending transmissions, cancel the watchdog 1385 * timer. 1386 */ 1387 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1388 ifp->if_timer = 0; 1389 } 1390 1391 /* 1392 * pcn_rxintr: 1393 * 1394 * Helper; handle receive interrupts. 1395 */ 1396 static int 1397 pcn_rxintr(struct pcn_softc *sc) 1398 { 1399 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1400 struct pcn_rxsoft *rxs; 1401 struct mbuf *m; 1402 uint32_t rmd1; 1403 int i, len; 1404 1405 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1406 rxs = &sc->sc_rxsoft[i]; 1407 1408 PCN_CDRXSYNC(sc, i, 1409 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1410 1411 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1412 1413 if (rmd1 & LE_R1_OWN) 1414 break; 1415 1416 /* 1417 * Check for errors and make sure the packet fit into 1418 * a single buffer. We have structured this block of 1419 * code the way it is in order to compress it into 1420 * one test in the common case (no error). 1421 */ 1422 if (__predict_false((rmd1 & (LE_R1_STP | LE_R1_ENP |LE_R1_ERR)) 1423 != (LE_R1_STP | LE_R1_ENP))) { 1424 /* Make sure the packet is in a single buffer. */ 1425 if ((rmd1 & (LE_R1_STP | LE_R1_ENP)) != 1426 (LE_R1_STP | LE_R1_ENP)) { 1427 printf("%s: packet spilled into next buffer\n", 1428 device_xname(sc->sc_dev)); 1429 return 1; /* pcn_intr() will re-init */ 1430 } 1431 1432 /* 1433 * If the packet had an error, simple recycle the 1434 * buffer. 1435 */ 1436 if (rmd1 & LE_R1_ERR) { 1437 if_statinc(ifp, if_ierrors); 1438 /* 1439 * If we got an overflow error, chances 1440 * are there will be a CRC error. In 1441 * this case, just print the overflow 1442 * error, and skip the others. 1443 */ 1444 if (rmd1 & LE_R1_OFLO) 1445 printf("%s: overflow error\n", 1446 device_xname(sc->sc_dev)); 1447 else { 1448 #define PRINTIT(x, str) \ 1449 if (rmd1 & (x)) \ 1450 printf("%s: %s\n", \ 1451 device_xname(sc->sc_dev), \ 1452 str); 1453 PRINTIT(LE_R1_FRAM, "framing error"); 1454 PRINTIT(LE_R1_CRC, "CRC error"); 1455 PRINTIT(LE_R1_BUFF, "buffer error"); 1456 } 1457 #undef PRINTIT 1458 PCN_INIT_RXDESC(sc, i); 1459 continue; 1460 } 1461 } 1462 1463 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1464 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1465 1466 /* 1467 * No errors; receive the packet. 1468 */ 1469 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1470 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1471 else 1472 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1473 1474 /* 1475 * The LANCE family includes the CRC with every packet; 1476 * trim it off here. 1477 */ 1478 len -= ETHER_CRC_LEN; 1479 1480 /* 1481 * If the packet is small enough to fit in a 1482 * single header mbuf, allocate one and copy 1483 * the data into it. This greatly reduces 1484 * memory consumption when we receive lots 1485 * of small packets. 1486 * 1487 * Otherwise, we add a new buffer to the receive 1488 * chain. If this fails, we drop the packet and 1489 * recycle the old buffer. 1490 */ 1491 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1492 MGETHDR(m, M_DONTWAIT, MT_DATA); 1493 if (m == NULL) 1494 goto dropit; 1495 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1496 m->m_data += 2; 1497 memcpy(mtod(m, void *), 1498 mtod(rxs->rxs_mbuf, void *), len); 1499 PCN_INIT_RXDESC(sc, i); 1500 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1501 rxs->rxs_dmamap->dm_mapsize, 1502 BUS_DMASYNC_PREREAD); 1503 } else { 1504 m = rxs->rxs_mbuf; 1505 if (pcn_add_rxbuf(sc, i) != 0) { 1506 dropit: 1507 if_statinc(ifp, if_ierrors); 1508 PCN_INIT_RXDESC(sc, i); 1509 bus_dmamap_sync(sc->sc_dmat, 1510 rxs->rxs_dmamap, 0, 1511 rxs->rxs_dmamap->dm_mapsize, 1512 BUS_DMASYNC_PREREAD); 1513 continue; 1514 } 1515 } 1516 1517 m_set_rcvif(m, ifp); 1518 m->m_pkthdr.len = m->m_len = len; 1519 1520 /* Pass it on. */ 1521 if_percpuq_enqueue(ifp->if_percpuq, m); 1522 } 1523 1524 /* Update the receive pointer. */ 1525 sc->sc_rxptr = i; 1526 return 0; 1527 } 1528 1529 /* 1530 * pcn_tick: 1531 * 1532 * One second timer, used to tick the MII. 1533 */ 1534 static void 1535 pcn_tick(void *arg) 1536 { 1537 struct pcn_softc *sc = arg; 1538 int s; 1539 1540 s = splnet(); 1541 mii_tick(&sc->sc_mii); 1542 splx(s); 1543 1544 callout_schedule(&sc->sc_tick_ch, hz); 1545 } 1546 1547 /* 1548 * pcn_reset: 1549 * 1550 * Perform a soft reset on the PCnet-PCI. 1551 */ 1552 static void 1553 pcn_reset(struct pcn_softc *sc) 1554 { 1555 1556 /* 1557 * The PCnet-PCI chip is reset by reading from the 1558 * RESET register. Note that while the NE2100 LANCE 1559 * boards require a write after the read, the PCnet-PCI 1560 * chips do not require this. 1561 * 1562 * Since we don't know if we're in 16-bit or 32-bit 1563 * mode right now, issue both (it's safe) in the 1564 * hopes that one will succeed. 1565 */ 1566 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1567 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1568 1569 /* Wait 1ms for it to finish. */ 1570 delay(1000); 1571 1572 /* 1573 * Select 32-bit I/O mode by issuing a 32-bit write to the 1574 * RDP. Since the RAP is 0 after a reset, writing a 0 1575 * to RDP is safe (since it simply clears CSR0). 1576 */ 1577 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1578 } 1579 1580 /* 1581 * pcn_init: [ifnet interface function] 1582 * 1583 * Initialize the interface. Must be called at splnet(). 1584 */ 1585 static int 1586 pcn_init(struct ifnet *ifp) 1587 { 1588 struct pcn_softc *sc = ifp->if_softc; 1589 struct pcn_rxsoft *rxs; 1590 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1591 int i, error = 0; 1592 uint32_t reg; 1593 1594 /* Cancel any pending I/O. */ 1595 pcn_stop(ifp, 0); 1596 1597 /* Reset the chip to a known state. */ 1598 pcn_reset(sc); 1599 1600 /* 1601 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1602 * else. 1603 * 1604 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1605 * because the structure layout is compatible with ILACC, 1606 * but the burst mode is only available in SSTYLE 3, and 1607 * burst mode should provide some performance enhancement. 1608 */ 1609 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1610 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1611 else 1612 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1613 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1614 1615 /* Initialize the transmit descriptor ring. */ 1616 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1617 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1618 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1619 sc->sc_txfree = PCN_NTXDESC; 1620 sc->sc_txnext = 0; 1621 1622 /* Initialize the transmit job descriptors. */ 1623 for (i = 0; i < PCN_TXQUEUELEN; i++) 1624 sc->sc_txsoft[i].txs_mbuf = NULL; 1625 sc->sc_txsfree = PCN_TXQUEUELEN; 1626 sc->sc_txsnext = 0; 1627 sc->sc_txsdirty = 0; 1628 1629 /* 1630 * Initialize the receive descriptor and receive job 1631 * descriptor rings. 1632 */ 1633 for (i = 0; i < PCN_NRXDESC; i++) { 1634 rxs = &sc->sc_rxsoft[i]; 1635 if (rxs->rxs_mbuf == NULL) { 1636 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1637 printf("%s: unable to allocate or map rx " 1638 "buffer %d, error = %d\n", 1639 device_xname(sc->sc_dev), i, error); 1640 /* 1641 * XXX Should attempt to run with fewer receive 1642 * XXX buffers instead of just failing. 1643 */ 1644 pcn_rxdrain(sc); 1645 goto out; 1646 } 1647 } else 1648 PCN_INIT_RXDESC(sc, i); 1649 } 1650 sc->sc_rxptr = 0; 1651 1652 /* Initialize MODE for the initialization block. */ 1653 sc->sc_mode = 0; 1654 if (ifp->if_flags & IFF_PROMISC) 1655 sc->sc_mode |= LE_C15_PROM; 1656 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1657 sc->sc_mode |= LE_C15_DRCVBC; 1658 1659 /* 1660 * If we have MII, simply select MII in the MODE register, 1661 * and clear ASEL. Otherwise, let ASEL stand (for now), 1662 * and leave PORTSEL alone (it is ignored with ASEL is set). 1663 */ 1664 if (sc->sc_flags & PCN_F_HAS_MII) { 1665 pcn_bcr_write(sc, LE_BCR2, 1666 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1667 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1668 1669 /* 1670 * Disable MII auto-negotiation. We handle that in 1671 * our own MII layer. 1672 */ 1673 pcn_bcr_write(sc, LE_BCR32, 1674 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1675 } 1676 1677 /* 1678 * Set the Tx and Rx descriptor ring addresses in the init 1679 * block, the TLEN and RLEN other fields of the init block 1680 * MODE register. 1681 */ 1682 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1683 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1684 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1685 (((uint32_t)ffs(PCN_NTXDESC) - 1) << 28) | 1686 ((ffs(PCN_NRXDESC) - 1) << 20)); 1687 1688 /* Set the station address in the init block. */ 1689 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1690 (enaddr[1] << 8) | (enaddr[2] << 16) | 1691 ((uint32_t)enaddr[3] << 24)); 1692 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1693 (enaddr[5] << 8)); 1694 1695 /* Set the multicast filter in the init block. */ 1696 pcn_set_filter(sc); 1697 1698 /* Initialize CSR3. */ 1699 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM | LE_C3_IDONM | LE_C3_DXSUFLO); 1700 1701 /* Initialize CSR4. */ 1702 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS | LE_C4_APAD_XMT | 1703 LE_C4_MFCOM | LE_C4_RCVCCOM | LE_C4_TXSTRTM); 1704 1705 /* Initialize CSR5. */ 1706 sc->sc_csr5 = LE_C5_LTINTEN | LE_C5_SINTE; 1707 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1708 1709 /* 1710 * If we have an Am79c971 or greater, initialize CSR7. 1711 * 1712 * XXX Might be nice to use the MII auto-poll interrupt someday. 1713 */ 1714 switch (sc->sc_variant->pcv_chipid) { 1715 case PARTID_Am79c970: 1716 case PARTID_Am79c970A: 1717 /* Not available on these chips. */ 1718 break; 1719 1720 default: 1721 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1722 break; 1723 } 1724 1725 /* 1726 * On the Am79c970A and greater, initialize BCR18 to 1727 * enable burst mode. 1728 * 1729 * Also enable the "no underflow" option on the Am79c971 and 1730 * higher, which prevents the chip from generating transmit 1731 * underflows, yet sill provides decent performance. Note if 1732 * chip is not connected to external SRAM, then we still have 1733 * to handle underflow errors (the NOUFLO bit is ignored in 1734 * that case). 1735 */ 1736 reg = pcn_bcr_read(sc, LE_BCR18); 1737 switch (sc->sc_variant->pcv_chipid) { 1738 case PARTID_Am79c970: 1739 break; 1740 1741 case PARTID_Am79c970A: 1742 reg |= LE_B18_BREADE | LE_B18_BWRITE; 1743 break; 1744 1745 default: 1746 reg |= LE_B18_BREADE | LE_B18_BWRITE | LE_B18_NOUFLO; 1747 break; 1748 } 1749 pcn_bcr_write(sc, LE_BCR18, reg); 1750 1751 /* 1752 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1753 */ 1754 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1755 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1756 1757 /* 1758 * Send the init block to the chip, and wait for it 1759 * to be processed. 1760 */ 1761 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1762 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1763 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1764 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1765 delay(100); 1766 for (i = 0; i < 10000; i++) { 1767 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1768 break; 1769 delay(10); 1770 } 1771 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1772 if (i == 10000) { 1773 printf("%s: timeout processing init block\n", 1774 device_xname(sc->sc_dev)); 1775 error = EIO; 1776 goto out; 1777 } 1778 1779 /* Set the media. */ 1780 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1781 goto out; 1782 1783 /* Enable interrupts and external activity (and ACK IDON). */ 1784 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_STRT | LE_C0_IDON); 1785 1786 if (sc->sc_flags & PCN_F_HAS_MII) { 1787 /* Start the one second MII clock. */ 1788 callout_schedule(&sc->sc_tick_ch, hz); 1789 } 1790 1791 /* ...all done! */ 1792 ifp->if_flags |= IFF_RUNNING; 1793 1794 out: 1795 if (error) 1796 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1797 return error; 1798 } 1799 1800 /* 1801 * pcn_rxdrain: 1802 * 1803 * Drain the receive queue. 1804 */ 1805 static void 1806 pcn_rxdrain(struct pcn_softc *sc) 1807 { 1808 struct pcn_rxsoft *rxs; 1809 int i; 1810 1811 for (i = 0; i < PCN_NRXDESC; i++) { 1812 rxs = &sc->sc_rxsoft[i]; 1813 if (rxs->rxs_mbuf != NULL) { 1814 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1815 m_freem(rxs->rxs_mbuf); 1816 rxs->rxs_mbuf = NULL; 1817 } 1818 } 1819 } 1820 1821 /* 1822 * pcn_stop: [ifnet interface function] 1823 * 1824 * Stop transmission on the interface. 1825 */ 1826 static void 1827 pcn_stop(struct ifnet *ifp, int disable) 1828 { 1829 struct pcn_softc *sc = ifp->if_softc; 1830 struct pcn_txsoft *txs; 1831 int i; 1832 1833 if (sc->sc_flags & PCN_F_HAS_MII) { 1834 /* Stop the one second clock. */ 1835 callout_stop(&sc->sc_tick_ch); 1836 1837 /* Down the MII. */ 1838 mii_down(&sc->sc_mii); 1839 } 1840 1841 /* Stop the chip. */ 1842 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1843 1844 /* Release any queued transmit buffers. */ 1845 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1846 txs = &sc->sc_txsoft[i]; 1847 if (txs->txs_mbuf != NULL) { 1848 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1849 m_freem(txs->txs_mbuf); 1850 txs->txs_mbuf = NULL; 1851 } 1852 } 1853 1854 /* Mark the interface as down and cancel the watchdog timer. */ 1855 ifp->if_flags &= ~IFF_RUNNING; 1856 ifp->if_timer = 0; 1857 1858 if (disable) 1859 pcn_rxdrain(sc); 1860 } 1861 1862 /* 1863 * pcn_add_rxbuf: 1864 * 1865 * Add a receive buffer to the indicated descriptor. 1866 */ 1867 static int 1868 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1869 { 1870 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1871 struct mbuf *m; 1872 int error; 1873 1874 MGETHDR(m, M_DONTWAIT, MT_DATA); 1875 if (m == NULL) 1876 return ENOBUFS; 1877 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1878 1879 MCLGET(m, M_DONTWAIT); 1880 if ((m->m_flags & M_EXT) == 0) { 1881 m_freem(m); 1882 return ENOBUFS; 1883 } 1884 1885 if (rxs->rxs_mbuf != NULL) 1886 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1887 1888 rxs->rxs_mbuf = m; 1889 1890 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1891 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1892 BUS_DMA_READ | BUS_DMA_NOWAIT); 1893 if (error) { 1894 printf("%s: can't load rx DMA map %d, error = %d\n", 1895 device_xname(sc->sc_dev), idx, error); 1896 panic("pcn_add_rxbuf"); 1897 } 1898 1899 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1900 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1901 1902 PCN_INIT_RXDESC(sc, idx); 1903 1904 return 0; 1905 } 1906 1907 /* 1908 * pcn_set_filter: 1909 * 1910 * Set up the receive filter. 1911 */ 1912 static void 1913 pcn_set_filter(struct pcn_softc *sc) 1914 { 1915 struct ethercom *ec = &sc->sc_ethercom; 1916 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1917 struct ether_multi *enm; 1918 struct ether_multistep step; 1919 uint32_t crc; 1920 1921 /* 1922 * Set up the multicast address filter by passing all multicast 1923 * addresses through a CRC generator, and then using the high 1924 * order 6 bits as an index into the 64-bit logical address 1925 * filter. The high order bits select the word, while the rest 1926 * of the bits select the bit within the word. 1927 */ 1928 1929 if (ifp->if_flags & IFF_PROMISC) 1930 goto allmulti; 1931 1932 sc->sc_initblock.init_ladrf[0] = 1933 sc->sc_initblock.init_ladrf[1] = 1934 sc->sc_initblock.init_ladrf[2] = 1935 sc->sc_initblock.init_ladrf[3] = 0; 1936 1937 ETHER_LOCK(ec); 1938 ETHER_FIRST_MULTI(step, ec, enm); 1939 while (enm != NULL) { 1940 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1941 /* 1942 * We must listen to a range of multicast addresses. 1943 * For now, just accept all multicasts, rather than 1944 * trying to set only those filter bits needed to match 1945 * the range. (At this time, the only use of address 1946 * ranges is for IP multicast routing, for which the 1947 * range is big enough to require all bits set.) 1948 */ 1949 ETHER_UNLOCK(ec); 1950 goto allmulti; 1951 } 1952 1953 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1954 1955 /* Just want the 6 most significant bits. */ 1956 crc >>= 26; 1957 1958 /* Set the corresponding bit in the filter. */ 1959 sc->sc_initblock.init_ladrf[crc >> 4] |= 1960 htole16(1 << (crc & 0xf)); 1961 1962 ETHER_NEXT_MULTI(step, enm); 1963 } 1964 ETHER_UNLOCK(ec); 1965 1966 ifp->if_flags &= ~IFF_ALLMULTI; 1967 return; 1968 1969 allmulti: 1970 ifp->if_flags |= IFF_ALLMULTI; 1971 sc->sc_initblock.init_ladrf[0] = 1972 sc->sc_initblock.init_ladrf[1] = 1973 sc->sc_initblock.init_ladrf[2] = 1974 sc->sc_initblock.init_ladrf[3] = 0xffff; 1975 } 1976 1977 /* 1978 * pcn_79c970_mediainit: 1979 * 1980 * Initialize media for the Am79c970. 1981 */ 1982 static void 1983 pcn_79c970_mediainit(struct pcn_softc *sc) 1984 { 1985 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1986 struct mii_data * const mii = &sc->sc_mii; 1987 const char *sep = ""; 1988 1989 mii->mii_ifp = ifp; 1990 1991 ifmedia_init(&mii->mii_media, IFM_IMASK, pcn_79c970_mediachange, 1992 pcn_79c970_mediastatus); 1993 1994 #define ADD(str, m, d) \ 1995 do { \ 1996 aprint_normal("%s%s", sep, str); \ 1997 ifmedia_add(&mii->mii_media, IFM_ETHER | (m), (d), NULL); \ 1998 sep = ", "; \ 1999 } while (/*CONSTCOND*/0) 2000 2001 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2002 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2003 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2004 ADD("10base5-FDX", IFM_10_5 | IFM_FDX, PORTSEL_AUI); 2005 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2006 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2007 ADD("10baseT-FDX", IFM_10_T | IFM_FDX, PORTSEL_10T); 2008 ADD("auto", IFM_AUTO, 0); 2009 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2010 ADD("auto-FDX", IFM_AUTO | IFM_FDX, 0); 2011 aprint_normal("\n"); 2012 2013 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2014 } 2015 2016 /* 2017 * pcn_79c970_mediastatus: [ifmedia interface function] 2018 * 2019 * Get the current interface media status (Am79c970 version). 2020 */ 2021 static void 2022 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2023 { 2024 struct pcn_softc *sc = ifp->if_softc; 2025 2026 /* 2027 * The currently selected media is always the active media. 2028 * Note: We have no way to determine what media the AUTO 2029 * process picked. 2030 */ 2031 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2032 } 2033 2034 /* 2035 * pcn_79c970_mediachange: [ifmedia interface function] 2036 * 2037 * Set hardware to newly-selected media (Am79c970 version). 2038 */ 2039 static int 2040 pcn_79c970_mediachange(struct ifnet *ifp) 2041 { 2042 struct pcn_softc *sc = ifp->if_softc; 2043 uint32_t reg; 2044 2045 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2046 /* 2047 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2048 */ 2049 reg = pcn_bcr_read(sc, LE_BCR2); 2050 reg |= LE_B2_ASEL; 2051 pcn_bcr_write(sc, LE_BCR2, reg); 2052 } else { 2053 /* 2054 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2055 */ 2056 reg = pcn_bcr_read(sc, LE_BCR2); 2057 reg &= ~LE_B2_ASEL; 2058 pcn_bcr_write(sc, LE_BCR2, reg); 2059 2060 reg = pcn_csr_read(sc, LE_CSR15); 2061 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2062 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2063 pcn_csr_write(sc, LE_CSR15, reg); 2064 } 2065 2066 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2067 reg = LE_B9_FDEN; 2068 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2069 reg |= LE_B9_AUIFD; 2070 pcn_bcr_write(sc, LE_BCR9, reg); 2071 } else 2072 pcn_bcr_write(sc, LE_BCR9, 0); 2073 2074 return 0; 2075 } 2076 2077 /* 2078 * pcn_79c971_mediainit: 2079 * 2080 * Initialize media for the Am79c971. 2081 */ 2082 static void 2083 pcn_79c971_mediainit(struct pcn_softc *sc) 2084 { 2085 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2086 struct mii_data * const mii = &sc->sc_mii; 2087 2088 /* We have MII. */ 2089 sc->sc_flags |= PCN_F_HAS_MII; 2090 2091 /* 2092 * The built-in 10BASE-T interface is mapped to the MII 2093 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2094 * word that tells us which PHY to use. 2095 * This driver used to ignore all but the first PHY to 2096 * answer, but this code was removed to support multiple 2097 * external PHYs. As the default instance will be the first 2098 * one to answer, no harm is done by letting the possibly 2099 * non-connected internal PHY show up. 2100 */ 2101 2102 /* Initialize our media structures and probe the MII. */ 2103 mii->mii_ifp = ifp; 2104 mii->mii_readreg = pcn_mii_readreg; 2105 mii->mii_writereg = pcn_mii_writereg; 2106 mii->mii_statchg = pcn_mii_statchg; 2107 2108 sc->sc_ethercom.ec_mii = mii; 2109 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 2110 2111 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 2112 MII_OFFSET_ANY, 0); 2113 if (LIST_FIRST(&mii->mii_phys) == NULL) { 2114 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 2115 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 2116 } else 2117 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2118 } 2119 2120 /* 2121 * pcn_mii_readreg: [mii interface function] 2122 * 2123 * Read a PHY register on the MII. 2124 */ 2125 static int 2126 pcn_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2127 { 2128 struct pcn_softc *sc = device_private(self); 2129 2130 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2131 *val = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2132 if (*val == 0xffff) 2133 return -1; 2134 2135 return 0; 2136 } 2137 2138 /* 2139 * pcn_mii_writereg: [mii interface function] 2140 * 2141 * Write a PHY register on the MII. 2142 */ 2143 static int 2144 pcn_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2145 { 2146 struct pcn_softc *sc = device_private(self); 2147 2148 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2149 pcn_bcr_write(sc, LE_BCR34, val); 2150 2151 return 0; 2152 } 2153 2154 /* 2155 * pcn_mii_statchg: [mii interface function] 2156 * 2157 * Callback from MII layer when media changes. 2158 */ 2159 static void 2160 pcn_mii_statchg(struct ifnet *ifp) 2161 { 2162 struct pcn_softc *sc = ifp->if_softc; 2163 2164 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2165 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2166 else 2167 pcn_bcr_write(sc, LE_BCR9, 0); 2168 } 2169
Indexes created Tue Oct 07 21:09:53 GMT 2025