1 /* $NetBSD: exynos5260-clk.h,v 1.1.1.2 2019/01/22 14:57:01 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * Author: Rahul Sharma <rahul.sharma (at) samsung.com> 7 * 8 * Provides Constants for Exynos5260 clocks. 9 */ 10 11 #ifndef _DT_BINDINGS_CLK_EXYNOS5260_H 12 #define _DT_BINDINGS_CLK_EXYNOS5260_H 13 14 /* Clock names: <cmu><type><IP> */ 15 16 /* List Of Clocks For CMU_TOP */ 17 18 #define TOP_FOUT_DISP_PLL 1 19 #define TOP_FOUT_AUD_PLL 2 20 #define TOP_MOUT_AUDTOP_PLL_USER 3 21 #define TOP_MOUT_AUD_PLL 4 22 #define TOP_MOUT_DISP_PLL 5 23 #define TOP_MOUT_BUSTOP_PLL_USER 6 24 #define TOP_MOUT_MEMTOP_PLL_USER 7 25 #define TOP_MOUT_MEDIATOP_PLL_USER 8 26 #define TOP_MOUT_DISP_DISP_333 9 27 #define TOP_MOUT_ACLK_DISP_333 10 28 #define TOP_MOUT_DISP_DISP_222 11 29 #define TOP_MOUT_ACLK_DISP_222 12 30 #define TOP_MOUT_DISP_MEDIA_PIXEL 13 31 #define TOP_MOUT_FIMD1 14 32 #define TOP_MOUT_SCLK_PERI_SPI0_CLK 15 33 #define TOP_MOUT_SCLK_PERI_SPI1_CLK 16 34 #define TOP_MOUT_SCLK_PERI_SPI2_CLK 17 35 #define TOP_MOUT_SCLK_PERI_UART0_UCLK 18 36 #define TOP_MOUT_SCLK_PERI_UART2_UCLK 19 37 #define TOP_MOUT_SCLK_PERI_UART1_UCLK 20 38 #define TOP_MOUT_BUS4_BUSTOP_100 21 39 #define TOP_MOUT_BUS4_BUSTOP_400 22 40 #define TOP_MOUT_BUS3_BUSTOP_100 23 41 #define TOP_MOUT_BUS3_BUSTOP_400 24 42 #define TOP_MOUT_BUS2_BUSTOP_400 25 43 #define TOP_MOUT_BUS2_BUSTOP_100 26 44 #define TOP_MOUT_BUS1_BUSTOP_100 27 45 #define TOP_MOUT_BUS1_BUSTOP_400 28 46 #define TOP_MOUT_SCLK_FSYS_USB 29 47 #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30 48 #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31 49 #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32 50 #define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33 51 #define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34 52 #define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35 53 #define TOP_MOUT_ACLK_ISP1_266 36 54 #define TOP_MOUT_ISP1_MEDIA_266 37 55 #define TOP_MOUT_ACLK_ISP1_400 38 56 #define TOP_MOUT_ISP1_MEDIA_400 39 57 #define TOP_MOUT_SCLK_ISP1_SPI0 40 58 #define TOP_MOUT_SCLK_ISP1_SPI1 41 59 #define TOP_MOUT_SCLK_ISP1_UART 42 60 #define TOP_MOUT_SCLK_ISP1_SENSOR2 43 61 #define TOP_MOUT_SCLK_ISP1_SENSOR1 44 62 #define TOP_MOUT_SCLK_ISP1_SENSOR0 45 63 #define TOP_MOUT_ACLK_MFC_333 46 64 #define TOP_MOUT_MFC_BUSTOP_333 47 65 #define TOP_MOUT_ACLK_G2D_333 48 66 #define TOP_MOUT_G2D_BUSTOP_333 49 67 #define TOP_MOUT_ACLK_GSCL_FIMC 50 68 #define TOP_MOUT_GSCL_BUSTOP_FIMC 51 69 #define TOP_MOUT_ACLK_GSCL_333 52 70 #define TOP_MOUT_GSCL_BUSTOP_333 53 71 #define TOP_MOUT_ACLK_GSCL_400 54 72 #define TOP_MOUT_M2M_MEDIATOP_400 55 73 #define TOP_DOUT_ACLK_MFC_333 56 74 #define TOP_DOUT_ACLK_G2D_333 57 75 #define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58 76 #define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59 77 #define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60 78 #define TOP_DOUT_ACLK_GSCL_FIMC 61 79 #define TOP_DOUT_ACLK_GSCL_400 62 80 #define TOP_DOUT_ACLK_GSCL_333 63 81 #define TOP_DOUT_SCLK_ISP1_SPI0_B 64 82 #define TOP_DOUT_SCLK_ISP1_SPI0_A 65 83 #define TOP_DOUT_ACLK_ISP1_400 66 84 #define TOP_DOUT_ACLK_ISP1_266 67 85 #define TOP_DOUT_SCLK_ISP1_UART 68 86 #define TOP_DOUT_SCLK_ISP1_SPI1_B 69 87 #define TOP_DOUT_SCLK_ISP1_SPI1_A 70 88 #define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71 89 #define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72 90 #define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73 91 #define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74 92 #define TOP_DOUT_SCLK_DISP_PIXEL 75 93 #define TOP_DOUT_ACLK_DISP_222 76 94 #define TOP_DOUT_ACLK_DISP_333 77 95 #define TOP_DOUT_ACLK_BUS4_100 78 96 #define TOP_DOUT_ACLK_BUS4_400 79 97 #define TOP_DOUT_ACLK_BUS3_100 80 98 #define TOP_DOUT_ACLK_BUS3_400 81 99 #define TOP_DOUT_ACLK_BUS2_100 82 100 #define TOP_DOUT_ACLK_BUS2_400 83 101 #define TOP_DOUT_ACLK_BUS1_100 84 102 #define TOP_DOUT_ACLK_BUS1_400 85 103 #define TOP_DOUT_SCLK_PERI_SPI1_B 86 104 #define TOP_DOUT_SCLK_PERI_SPI1_A 87 105 #define TOP_DOUT_SCLK_PERI_SPI0_B 88 106 #define TOP_DOUT_SCLK_PERI_SPI0_A 89 107 #define TOP_DOUT_SCLK_PERI_UART0 90 108 #define TOP_DOUT_SCLK_PERI_UART2 91 109 #define TOP_DOUT_SCLK_PERI_UART1 92 110 #define TOP_DOUT_SCLK_PERI_SPI2_B 93 111 #define TOP_DOUT_SCLK_PERI_SPI2_A 94 112 #define TOP_DOUT_ACLK_PERI_AUD 95 113 #define TOP_DOUT_ACLK_PERI_66 96 114 #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97 115 #define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98 116 #define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99 117 #define TOP_DOUT_ACLK_FSYS_200 100 118 #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101 119 #define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102 120 #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103 121 #define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104 122 #define TOP_SCLK_FIMD1 105 123 #define TOP_SCLK_MMC2 106 124 #define TOP_SCLK_MMC1 107 125 #define TOP_SCLK_MMC0 108 126 #define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109 127 #define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110 128 #define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111 129 #define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112 130 #define phyclk_hdmi_phy_tmds_clko 113 131 #define PHYCLK_HDMI_PHY_PIXEL_CLKO 114 132 #define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115 133 #define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116 134 #define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117 135 #define PHYCLK_DPTX_PHY_CLK_DIV2 118 136 #define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119 137 #define PHYCLK_USBHOST20_PHY_PHYCLOCK 120 138 #define PHYCLK_USBHOST20_PHY_FREECLK 121 139 #define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122 140 #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123 141 #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124 142 #define TOP_NR_CLK 125 143 144 145 /* List Of Clocks For CMU_EGL */ 146 147 #define EGL_FOUT_EGL_PLL 1 148 #define EGL_FOUT_EGL_DPLL 2 149 #define EGL_MOUT_EGL_B 3 150 #define EGL_MOUT_EGL_PLL 4 151 #define EGL_DOUT_EGL_PLL 5 152 #define EGL_DOUT_EGL_PCLK_DBG 6 153 #define EGL_DOUT_EGL_ATCLK 7 154 #define EGL_DOUT_PCLK_EGL 8 155 #define EGL_DOUT_ACLK_EGL 9 156 #define EGL_DOUT_EGL2 10 157 #define EGL_DOUT_EGL1 11 158 #define EGL_NR_CLK 12 159 160 161 /* List Of Clocks For CMU_KFC */ 162 163 #define KFC_FOUT_KFC_PLL 1 164 #define KFC_MOUT_KFC_PLL 2 165 #define KFC_MOUT_KFC 3 166 #define KFC_DOUT_KFC_PLL 4 167 #define KFC_DOUT_PCLK_KFC 5 168 #define KFC_DOUT_ACLK_KFC 6 169 #define KFC_DOUT_KFC_PCLK_DBG 7 170 #define KFC_DOUT_KFC_ATCLK 8 171 #define KFC_DOUT_KFC2 9 172 #define KFC_DOUT_KFC1 10 173 #define KFC_NR_CLK 11 174 175 176 /* List Of Clocks For CMU_MIF */ 177 178 #define MIF_FOUT_MEM_PLL 1 179 #define MIF_FOUT_MEDIA_PLL 2 180 #define MIF_FOUT_BUS_PLL 3 181 #define MIF_MOUT_CLK2X_PHY 4 182 #define MIF_MOUT_MIF_DREX2X 5 183 #define MIF_MOUT_CLKM_PHY 6 184 #define MIF_MOUT_MIF_DREX 7 185 #define MIF_MOUT_MEDIA_PLL 8 186 #define MIF_MOUT_BUS_PLL 9 187 #define MIF_MOUT_MEM_PLL 10 188 #define MIF_DOUT_ACLK_BUS_100 11 189 #define MIF_DOUT_ACLK_BUS_200 12 190 #define MIF_DOUT_ACLK_MIF_466 13 191 #define MIF_DOUT_CLK2X_PHY 14 192 #define MIF_DOUT_CLKM_PHY 15 193 #define MIF_DOUT_BUS_PLL 16 194 #define MIF_DOUT_MEM_PLL 17 195 #define MIF_DOUT_MEDIA_PLL 18 196 #define MIF_CLK_LPDDR3PHY_WRAP1 19 197 #define MIF_CLK_LPDDR3PHY_WRAP0 20 198 #define MIF_CLK_MONOCNT 21 199 #define MIF_CLK_MIF_RTC 22 200 #define MIF_CLK_DREX1 23 201 #define MIF_CLK_DREX0 24 202 #define MIF_CLK_INTMEM 25 203 #define MIF_SCLK_LPDDR3PHY_WRAP_U1 26 204 #define MIF_SCLK_LPDDR3PHY_WRAP_U0 27 205 #define MIF_NR_CLK 28 206 207 208 /* List Of Clocks For CMU_G3D */ 209 210 #define G3D_FOUT_G3D_PLL 1 211 #define G3D_MOUT_G3D_PLL 2 212 #define G3D_DOUT_PCLK_G3D 3 213 #define G3D_DOUT_ACLK_G3D 4 214 #define G3D_CLK_G3D_HPM 5 215 #define G3D_CLK_G3D 6 216 #define G3D_NR_CLK 7 217 218 219 /* List Of Clocks For CMU_AUD */ 220 221 #define AUD_MOUT_SCLK_AUD_PCM 1 222 #define AUD_MOUT_SCLK_AUD_I2S 2 223 #define AUD_MOUT_AUD_PLL_USER 3 224 #define AUD_DOUT_ACLK_AUD_131 4 225 #define AUD_DOUT_SCLK_AUD_UART 5 226 #define AUD_DOUT_SCLK_AUD_PCM 6 227 #define AUD_DOUT_SCLK_AUD_I2S 7 228 #define AUD_CLK_AUD_UART 8 229 #define AUD_CLK_PCM 9 230 #define AUD_CLK_I2S 10 231 #define AUD_CLK_DMAC 11 232 #define AUD_CLK_SRAMC 12 233 #define AUD_SCLK_AUD_UART 13 234 #define AUD_SCLK_PCM 14 235 #define AUD_SCLK_I2S 15 236 #define AUD_NR_CLK 16 237 238 239 /* List Of Clocks For CMU_MFC */ 240 241 #define MFC_MOUT_ACLK_MFC_333_USER 1 242 #define MFC_DOUT_PCLK_MFC_83 2 243 #define MFC_CLK_MFC 3 244 #define MFC_CLK_SMMU2_MFCM1 4 245 #define MFC_CLK_SMMU2_MFCM0 5 246 #define MFC_NR_CLK 6 247 248 249 /* List Of Clocks For CMU_GSCL */ 250 251 #define GSCL_MOUT_ACLK_CSIS 1 252 #define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2 253 #define GSCL_MOUT_ACLK_M2M_400_USER 3 254 #define GSCL_MOUT_ACLK_GSCL_333_USER 4 255 #define GSCL_DOUT_ACLK_CSIS_200 5 256 #define GSCL_DOUT_PCLK_M2M_100 6 257 #define GSCL_CLK_PIXEL_GSCL1 7 258 #define GSCL_CLK_PIXEL_GSCL0 8 259 #define GSCL_CLK_MSCL1 9 260 #define GSCL_CLK_MSCL0 10 261 #define GSCL_CLK_GSCL1 11 262 #define GSCL_CLK_GSCL0 12 263 #define GSCL_CLK_FIMC_LITE_D 13 264 #define GSCL_CLK_FIMC_LITE_B 14 265 #define GSCL_CLK_FIMC_LITE_A 15 266 #define GSCL_CLK_CSIS1 16 267 #define GSCL_CLK_CSIS0 17 268 #define GSCL_CLK_SMMU3_LITE_D 18 269 #define GSCL_CLK_SMMU3_LITE_B 19 270 #define GSCL_CLK_SMMU3_LITE_A 20 271 #define GSCL_CLK_SMMU3_GSCL0 21 272 #define GSCL_CLK_SMMU3_GSCL1 22 273 #define GSCL_CLK_SMMU3_MSCL0 23 274 #define GSCL_CLK_SMMU3_MSCL1 24 275 #define GSCL_SCLK_CSIS1_WRAP 25 276 #define GSCL_SCLK_CSIS0_WRAP 26 277 #define GSCL_NR_CLK 27 278 279 280 /* List Of Clocks For CMU_FSYS */ 281 282 #define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1 283 #define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2 284 #define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3 285 #define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4 286 #define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5 287 #define FSYS_CLK_TSI 6 288 #define FSYS_CLK_USBLINK 7 289 #define FSYS_CLK_USBHOST20 8 290 #define FSYS_CLK_USBDRD30 9 291 #define FSYS_CLK_SROMC 10 292 #define FSYS_CLK_PDMA 11 293 #define FSYS_CLK_MMC2 12 294 #define FSYS_CLK_MMC1 13 295 #define FSYS_CLK_MMC0 14 296 #define FSYS_CLK_RTIC 15 297 #define FSYS_CLK_SMMU_RTIC 16 298 #define FSYS_PHYCLK_USBDRD30 17 299 #define FSYS_PHYCLK_USBHOST20 18 300 #define FSYS_NR_CLK 19 301 302 303 /* List Of Clocks For CMU_PERI */ 304 305 #define PERI_MOUT_SCLK_SPDIF 1 306 #define PERI_MOUT_SCLK_I2SCOD 2 307 #define PERI_MOUT_SCLK_PCM 3 308 #define PERI_DOUT_I2S 4 309 #define PERI_DOUT_PCM 5 310 #define PERI_CLK_WDT_KFC 6 311 #define PERI_CLK_WDT_EGL 7 312 #define PERI_CLK_HSIC3 8 313 #define PERI_CLK_HSIC2 9 314 #define PERI_CLK_HSIC1 10 315 #define PERI_CLK_HSIC0 11 316 #define PERI_CLK_PCM 12 317 #define PERI_CLK_MCT 13 318 #define PERI_CLK_I2S 14 319 #define PERI_CLK_I2CHDMI 15 320 #define PERI_CLK_I2C7 16 321 #define PERI_CLK_I2C6 17 322 #define PERI_CLK_I2C5 18 323 #define PERI_CLK_I2C4 19 324 #define PERI_CLK_I2C9 20 325 #define PERI_CLK_I2C8 21 326 #define PERI_CLK_I2C11 22 327 #define PERI_CLK_I2C10 23 328 #define PERI_CLK_HDMICEC 24 329 #define PERI_CLK_EFUSE_WRITER 25 330 #define PERI_CLK_ABB 26 331 #define PERI_CLK_UART2 27 332 #define PERI_CLK_UART1 28 333 #define PERI_CLK_UART0 29 334 #define PERI_CLK_ADC 30 335 #define PERI_CLK_TMU4 31 336 #define PERI_CLK_TMU3 32 337 #define PERI_CLK_TMU2 33 338 #define PERI_CLK_TMU1 34 339 #define PERI_CLK_TMU0 35 340 #define PERI_CLK_SPI2 36 341 #define PERI_CLK_SPI1 37 342 #define PERI_CLK_SPI0 38 343 #define PERI_CLK_SPDIF 39 344 #define PERI_CLK_PWM 40 345 #define PERI_CLK_UART4 41 346 #define PERI_CLK_CHIPID 42 347 #define PERI_CLK_PROVKEY0 43 348 #define PERI_CLK_PROVKEY1 44 349 #define PERI_CLK_SECKEY 45 350 #define PERI_CLK_TOP_RTC 46 351 #define PERI_CLK_TZPC10 47 352 #define PERI_CLK_TZPC9 48 353 #define PERI_CLK_TZPC8 49 354 #define PERI_CLK_TZPC7 50 355 #define PERI_CLK_TZPC6 51 356 #define PERI_CLK_TZPC5 52 357 #define PERI_CLK_TZPC4 53 358 #define PERI_CLK_TZPC3 54 359 #define PERI_CLK_TZPC2 55 360 #define PERI_CLK_TZPC1 56 361 #define PERI_CLK_TZPC0 57 362 #define PERI_SCLK_UART2 58 363 #define PERI_SCLK_UART1 59 364 #define PERI_SCLK_UART0 60 365 #define PERI_SCLK_SPI2 61 366 #define PERI_SCLK_SPI1 62 367 #define PERI_SCLK_SPI0 63 368 #define PERI_SCLK_SPDIF 64 369 #define PERI_SCLK_I2S 65 370 #define PERI_SCLK_PCM1 66 371 #define PERI_NR_CLK 67 372 373 374 /* List Of Clocks For CMU_DISP */ 375 376 #define DISP_MOUT_SCLK_HDMI_SPDIF 1 377 #define DISP_MOUT_SCLK_HDMI_PIXEL 2 378 #define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3 379 #define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4 380 #define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5 381 #define DISP_MOUT_HDMI_PHY_PIXEL 6 382 #define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7 383 #define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8 384 #define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9 385 #define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10 386 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11 387 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12 388 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13 389 #define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14 390 #define DISP_MOUT_ACLK_DISP_222_USER 15 391 #define DISP_MOUT_SCLK_DISP_PIXEL_USER 16 392 #define DISP_MOUT_ACLK_DISP_333_USER 17 393 #define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18 394 #define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19 395 #define DISP_DOUT_PCLK_DISP_111 20 396 #define DISP_CLK_SMMU_TV 21 397 #define DISP_CLK_SMMU_FIMD1M1 22 398 #define DISP_CLK_SMMU_FIMD1M0 23 399 #define DISP_CLK_PIXEL_MIXER 24 400 #define DISP_CLK_PIXEL_DISP 25 401 #define DISP_CLK_MIXER 26 402 #define DISP_CLK_MIPIPHY 27 403 #define DISP_CLK_HDMIPHY 28 404 #define DISP_CLK_HDMI 29 405 #define DISP_CLK_FIMD1 30 406 #define DISP_CLK_DSIM1 31 407 #define DISP_CLK_DPPHY 32 408 #define DISP_CLK_DP 33 409 #define DISP_SCLK_PIXEL 34 410 #define DISP_MOUT_HDMI_PHY_PIXEL_USER 35 411 #define DISP_NR_CLK 36 412 413 414 /* List Of Clocks For CMU_G2D */ 415 416 #define G2D_MOUT_ACLK_G2D_333_USER 1 417 #define G2D_DOUT_PCLK_G2D_83 2 418 #define G2D_CLK_SMMU3_JPEG 3 419 #define G2D_CLK_MDMA 4 420 #define G2D_CLK_JPEG 5 421 #define G2D_CLK_G2D 6 422 #define G2D_CLK_SSS 7 423 #define G2D_CLK_SLIM_SSS 8 424 #define G2D_CLK_SMMU_SLIM_SSS 9 425 #define G2D_CLK_SMMU_SSS 10 426 #define G2D_CLK_SMMU_MDMA 11 427 #define G2D_CLK_SMMU3_G2D 12 428 #define G2D_NR_CLK 13 429 430 431 /* List Of Clocks For CMU_ISP */ 432 433 #define ISP_MOUT_ISP_400_USER 1 434 #define ISP_MOUT_ISP_266_USER 2 435 #define ISP_DOUT_SCLK_MPWM 3 436 #define ISP_DOUT_CA5_PCLKDBG 4 437 #define ISP_DOUT_CA5_ATCLKIN 5 438 #define ISP_DOUT_PCLK_ISP_133 6 439 #define ISP_DOUT_PCLK_ISP_66 7 440 #define ISP_CLK_GIC 8 441 #define ISP_CLK_WDT 9 442 #define ISP_CLK_UART 10 443 #define ISP_CLK_SPI1 11 444 #define ISP_CLK_SPI0 12 445 #define ISP_CLK_SMMU_SCALERP 13 446 #define ISP_CLK_SMMU_SCALERC 14 447 #define ISP_CLK_SMMU_ISPCX 15 448 #define ISP_CLK_SMMU_ISP 16 449 #define ISP_CLK_SMMU_FD 17 450 #define ISP_CLK_SMMU_DRC 18 451 #define ISP_CLK_PWM 19 452 #define ISP_CLK_MTCADC 20 453 #define ISP_CLK_MPWM 21 454 #define ISP_CLK_MCUCTL 22 455 #define ISP_CLK_I2C1 23 456 #define ISP_CLK_I2C0 24 457 #define ISP_CLK_FIMC_SCALERP 25 458 #define ISP_CLK_FIMC_SCALERC 26 459 #define ISP_CLK_FIMC 27 460 #define ISP_CLK_FIMC_FD 28 461 #define ISP_CLK_FIMC_DRC 29 462 #define ISP_CLK_CA5 30 463 #define ISP_SCLK_SPI0_EXT 31 464 #define ISP_SCLK_SPI1_EXT 32 465 #define ISP_SCLK_UART_EXT 33 466 #define ISP_NR_CLK 34 467 468 #endif 469
Indexes created Wed Oct 01 15:09:59 GMT 2025