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      1 /*	$NetBSD: qat_c2xxxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2019 Internet Initiative Japan, Inc.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 /*
     30  *   Copyright(c) 2007-2013 Intel Corporation. All rights reserved.
     31  *
     32  *   Redistribution and use in source and binary forms, with or without
     33  *   modification, are permitted provided that the following conditions
     34  *   are met:
     35  *
     36  *     * Redistributions of source code must retain the above copyright
     37  *       notice, this list of conditions and the following disclaimer.
     38  *     * Redistributions in binary form must reproduce the above copyright
     39  *       notice, this list of conditions and the following disclaimer in
     40  *       the documentation and/or other materials provided with the
     41  *       distribution.
     42  *     * Neither the name of Intel Corporation nor the names of its
     43  *       contributors may be used to endorse or promote products derived
     44  *       from this software without specific prior written permission.
     45  *
     46  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     47  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
     48  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
     49  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
     50  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     51  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     52  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     53  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     54  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     55  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     56  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     57  */
     58 
     59 #ifndef _DEV_PCI_QAT_C2XXXREG_H_
     60 #define _DEV_PCI_QAT_C2XXXREG_H_
     61 
     62 /* PCI revision IDs */
     63 #define QAT_REVID_C2XXX_A0		0x00
     64 #define QAT_REVID_C2XXX_B0		0x02
     65 #define QAT_REVID_C2XXX_C0		0x03
     66 
     67 /* Max number of accelerators and engines */
     68 #define MAX_ACCEL_C2XXX			1
     69 #define MAX_AE_C2XXX			2
     70 
     71 /* PCIe BAR index */
     72 #define BAR_SRAM_ID_C2XXX		NO_PCI_REG
     73 #define BAR_PMISC_ID_C2XXX		0
     74 #define BAR_ETR_ID_C2XXX		1
     75 
     76 #define ACCEL_MASK_C2XXX		0x1
     77 #define AE_MASK_C2XXX			0x3
     78 
     79 #define MSIX_AE_VEC_GAP_C2XXX		8
     80 
     81 /* PCIe configuration space registers */
     82 /* PESRAM: 512K eSRAM */
     83 #define BAR_PESRAM_C2XXX		NO_PCI_REG
     84 #define BAR_PESRAM_SIZE_C2XXX		0
     85 
     86 /*
     87  * PMISC: 16K CAP, 16K Scratch, 32K SSU(QATs),
     88  *        32K AE CSRs and transfer registers, 8K CHAP/PMU,
     89  *        4K EP CSRs, 4K MSI-X Tables
     90  */
     91 #define BAR_PMISC_C2XXX			0x18
     92 #define BAR_PMISC_SIZE_C2XXX		0x20000	/* 128K */
     93 
     94 /* PETRINGCSR: 8K 16 bundles of ET Ring CSRs */
     95 #define BAR_PETRINGCSR_C2XXX		0x20
     96 #define BAR_PETRINGCSR_SIZE_C2XXX	0x4000	/* 16K */
     97 
     98 /* Fuse Control */
     99 #define FUSECTL_C2XXX_PKE_DISABLE	(1 << 6)
    100 #define FUSECTL_C2XXX_ATH_DISABLE	(1 << 5)
    101 #define FUSECTL_C2XXX_CPH_DISABLE	(1 << 4)
    102 #define FUSECTL_C2XXX_LOW_SKU		(1 << 3)
    103 #define FUSECTL_C2XXX_MID_SKU		(1 << 2)
    104 #define FUSECTL_C2XXX_AE1_DISABLE	(1 << 1)
    105 
    106 /* SINT: Signal Target Raw Interrupt Register */
    107 #define EP_SINTPF_C2XXX			0x1A024
    108 
    109 /* SMIA: Signal Target IA Mask Register */
    110 #define EP_SMIA_C2XXX				0x1A028
    111 #define EP_SMIA_BUNDLES_IRQ_MASK_C2XXX		0xFF
    112 #define EP_SMIA_AE_IRQ_MASK_C2XXX		0x10000
    113 #define EP_SMIA_MASK_C2XXX			\
    114 	(EP_SMIA_BUNDLES_IRQ_MASK_C2XXX | EP_SMIA_AE_IRQ_MASK_C2XXX)
    115 
    116 #define EP_RIMISCCTL_C2XXX		0x1A0C4
    117 #define EP_RIMISCCTL_MASK_C2XXX		0x40000000
    118 
    119 #define PFCGCIOSFPRIR_REG_C2XXX			0x2C0
    120 #define PFCGCIOSFPRIR_MASK_C2XXX		0XFFFF7FFF
    121 
    122 /* BAR sub-regions */
    123 #define PESRAM_BAR_C2XXX		NO_PCI_REG
    124 #define PESRAM_OFFSET_C2XXX		0x0
    125 #define PESRAM_SIZE_C2XXX		0x0
    126 #define CAP_GLOBAL_BAR_C2XXX		BAR_PMISC_C2XXX
    127 #define CAP_GLOBAL_OFFSET_C2XXX		0x00000
    128 #define CAP_GLOBAL_SIZE_C2XXX		0x04000
    129 #define CAP_HASH_OFFSET			0x900
    130 #define SCRATCH_BAR_C2XXX		NO_PCI_REG
    131 #define SCRATCH_OFFSET_C2XXX		NO_REG_OFFSET
    132 #define SCRATCH_SIZE_C2XXX		0x0
    133 #define SSU_BAR_C2XXX			BAR_PMISC_C2XXX
    134 #define SSU_OFFSET_C2XXX		0x08000
    135 #define SSU_SIZE_C2XXX			0x08000
    136 #define AE_BAR_C2XXX			BAR_PMISC_C2XXX
    137 #define AE_OFFSET_C2XXX			0x10000
    138 #define AE_LOCAL_OFFSET_C2XXX		0x10800
    139 #define PMU_BAR_C2XXX			NO_PCI_REG
    140 #define PMU_OFFSET_C2XXX		NO_REG_OFFSET
    141 #define PMU_SIZE_C2XXX			0x0
    142 #define EP_BAR_C2XXX			BAR_PMISC_C2XXX
    143 #define EP_OFFSET_C2XXX			0x1A000
    144 #define EP_SIZE_C2XXX			0x01000
    145 #define MSIX_TAB_BAR_C2XXX		NO_PCI_REG	/* mapped by pci(9) */
    146 #define MSIX_TAB_OFFSET_C2XXX		0x1B000
    147 #define MSIX_TAB_SIZE_C2XXX		0x01000
    148 #define PETRINGCSR_BAR_C2XXX		BAR_PETRINGCSR_C2XXX
    149 #define PETRINGCSR_OFFSET_C2XXX		0x0
    150 #define PETRINGCSR_SIZE_C2XXX		0x0	/* use size of BAR */
    151 
    152 /* ETR */
    153 #define ETR_MAX_BANKS_C2XXX		8
    154 #define ETR_MAX_ET_RINGS_C2XXX		\
    155 	(ETR_MAX_BANKS_C2XXX * ETR_MAX_RINGS_PER_BANK_C2XXX)
    156 #define ETR_MAX_AP_BANKS_C2XXX		4
    157 
    158 #define ETR_TX_RX_GAP_C2XXX		1
    159 #define ETR_TX_RINGS_MASK_C2XXX		0x51
    160 
    161 #define ETR_BUNDLE_SIZE_C2XXX		0x0200
    162 
    163 /* Initial bank Interrupt Source mask */
    164 #define ETR_INT_SRCSEL_MASK_0_C2XXX	0x4444444CUL
    165 #define ETR_INT_SRCSEL_MASK_X_C2XXX	0x44444444UL
    166 
    167 /* AE firmware */
    168 #define AE_FW_PROD_TYPE_C2XXX			0x00800000
    169 #define AE_FW_MOF_NAME_C2XXX		"mof_firmware_c2xxx.bin"
    170 #define AE_FW_MMP_NAME_C2XXX		"mmp_firmware_c2xxx.bin"
    171 #define AE_FW_UOF_NAME_C2XXX_A0		"icp_qat_nae.uof"
    172 #define AE_FW_UOF_NAME_C2XXX_B0		"icp_qat_nae_b0.uof"
    173 
    174 #endif
    175