Searched defs:PIPE_CONTROL_STATE_CACHE_INVALIDATE (Results 1 - 1 of 1) sorted by relevance

/src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_gpu_commands.h248 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) macro

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