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    Searched defs:PSW (Results 1 - 25 of 28) sorted by relevancy

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  /src/external/gpl3/binutils/dist/opcodes/
m10200-opc.c 97 #define PSW (IMM24_MEM+1)
101 #define MDR (PSW+1)
172 { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
173 { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
284 { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
288 { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
m10300-opc.c 147 #define PSW (SP+1)
151 #define MDR (PSW+1)
458 { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
459 { "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}},
857 { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
869 { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
ppc-opc.c 3203 #define PSW E
9190 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
9196 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
9658 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
9666 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
  /src/external/gpl3/binutils.old/dist/opcodes/
m10200-opc.c 97 #define PSW (IMM24_MEM+1)
101 #define MDR (PSW+1)
172 { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
173 { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
284 { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
288 { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
m10300-opc.c 147 #define PSW (SP+1)
151 #define MDR (PSW+1)
458 { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
459 { "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}},
857 { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
869 { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
  /src/external/gpl3/gdb/dist/opcodes/
m10200-opc.c 97 #define PSW (IMM24_MEM+1)
101 #define MDR (PSW+1)
172 { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
173 { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
284 { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
288 { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
m10300-opc.c 147 #define PSW (SP+1)
151 #define MDR (PSW+1)
458 { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
459 { "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}},
857 { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
869 { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
  /src/external/gpl3/gdb.old/dist/opcodes/
m10200-opc.c 97 #define PSW (IMM24_MEM+1)
101 #define MDR (PSW+1)
172 { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
173 { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
284 { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
288 { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
m10300-opc.c 147 #define PSW (SP+1)
151 #define MDR (PSW+1)
458 { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
459 { "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}},
857 { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
869 { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
  /src/external/gpl3/binutils/dist/include/opcode/
convex.h 49 #define PSW 8
76 "psw",
463 {0,0,lr,PSW,A,0}, /* mov */
464 {0,0,rxl,A,PSW,0}, /* mov */
  /src/external/gpl3/binutils.old/dist/include/opcode/
convex.h 49 #define PSW 8
76 "psw",
463 {0,0,lr,PSW,A,0}, /* mov */
464 {0,0,rxl,A,PSW,0}, /* mov */
  /src/external/gpl3/gdb/dist/include/opcode/
convex.h 49 #define PSW 8
76 "psw",
463 {0,0,lr,PSW,A,0}, /* mov */
464 {0,0,rxl,A,PSW,0}, /* mov */
  /src/external/gpl3/gdb.old/dist/include/opcode/
convex.h 49 #define PSW 8
76 "psw",
463 {0,0,lr,PSW,A,0}, /* mov */
464 {0,0,rxl,A,PSW,0}, /* mov */
  /src/external/gpl3/gdb/dist/sim/mn10300/
mn10300-sim.h 29 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
54 #define PSW (State.regs[11])
62 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
117 #define FPU_DISABLED !(PSW & PSW_FE)
  /src/external/gpl3/gdb.old/dist/sim/mn10300/
mn10300-sim.h 29 reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
54 #define PSW (State.regs[11])
62 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
117 #define FPU_DISABLED !(PSW & PSW_FE)
  /src/external/gpl3/binutils/dist/gas/config/
rl78-parse.h 71 PSW = 272, /* PSW */
196 #define PSW 272
rl78-parse.c 257 PSW = 272, /* PSW */
382 #define PSW 272
532 YYSYMBOL_PSW = 17, /* PSW */
1146 "D", "E", "H", "L", "AX", "BC", "DE", "HL", "SPL", "SPH", "PSW", "CS",
3601 case 224: /* statement: POP PSW */
3613 case 226: /* statement: PUSH PSW */
4043 case 292: /* sfr: PSW */
4483 { "psw", PSW, 0xfa }
    [all...]
  /src/external/gpl3/binutils.old/dist/gas/config/
rl78-parse.h 71 PSW = 272, /* PSW */
196 #define PSW 272
rl78-parse.c 257 PSW = 272, /* PSW */
382 #define PSW 272
532 YYSYMBOL_PSW = 17, /* PSW */
1146 "D", "E", "H", "L", "AX", "BC", "DE", "HL", "SPL", "SPH", "PSW", "CS",
3601 case 224: /* statement: POP PSW */
3613 case 226: /* statement: PUSH PSW */
4043 case 292: /* sfr: PSW */
4483 { "psw", PSW, 0xfa }
    [all...]
  /src/external/gpl3/gdb/dist/gdb/stubs/
m32r-stub.c 123 PSW, CBR, SPI, SPU, BPC, PC, ACCL, ACCH
414 stackmode = registers[PSW] & 0x80;
432 else if (regno == PSW) /* stack mode may have changed! */
1249 { /* separate out the bit flags in the PSW register */
1259 } *psw; variable in typeref:struct:PSWreg
1293 st r0, @+r1 ; cr0 == PSW\n\
1317 psw = (struct PSWreg *) &registers[PSW]; /* fields of PSW register */
1318 psw->sm = psw->bsm; /* fix up pre-trap values of psw fields *
    [all...]
  /src/external/gpl3/gdb.old/dist/gdb/stubs/
m32r-stub.c 123 PSW, CBR, SPI, SPU, BPC, PC, ACCL, ACCH
414 stackmode = registers[PSW] & 0x80;
432 else if (regno == PSW) /* stack mode may have changed! */
1249 { /* separate out the bit flags in the PSW register */
1259 } *psw; variable in typeref:struct:PSWreg
1293 st r0, @+r1 ; cr0 == PSW\n\
1317 psw = (struct PSWreg *) &registers[PSW]; /* fields of PSW register */
1318 psw->sm = psw->bsm; /* fix up pre-trap values of psw fields *
    [all...]
  /src/external/gpl3/gdb/dist/sim/d10v/
d10v-sim.h 254 uint16_t psw; member in struct:_state::__anon19325
307 #define PSW CREG (PSW_CR)
312 #define PSW_SM ((PSW & PSW_SM_BIT) != 0)
315 #define PSW_EA ((PSW & PSW_EA_BIT) != 0)
318 #define PSW_DB ((PSW & PSW_DB_BIT) != 0)
321 #define PSW_DM ((PSW & PSW_DM_BIT) != 0)
324 #define PSW_IE ((PSW & PSW_IE_BIT) != 0)
327 #define PSW_RP ((PSW & PSW_RP_BIT) != 0)
330 #define PSW_MD ((PSW & PSW_MD_BIT) != 0)
333 #define PSW_FX ((PSW & PSW_FX_BIT) != 0
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/d10v/
d10v-sim.h 254 uint16_t psw; member in struct:_state::__anon22064
307 #define PSW CREG (PSW_CR)
312 #define PSW_SM ((PSW & PSW_SM_BIT) != 0)
315 #define PSW_EA ((PSW & PSW_EA_BIT) != 0)
318 #define PSW_DB ((PSW & PSW_DB_BIT) != 0)
321 #define PSW_DM ((PSW & PSW_DM_BIT) != 0)
324 #define PSW_IE ((PSW & PSW_IE_BIT) != 0)
327 #define PSW_RP ((PSW & PSW_RP_BIT) != 0)
330 #define PSW_MD ((PSW & PSW_MD_BIT) != 0)
333 #define PSW_FX ((PSW & PSW_FX_BIT) != 0
    [all...]
  /src/external/gpl3/gdb/dist/sim/v850/
v850-sim.h 25 reg_t sregs[32]; /* system registers, including psw */
110 #define PSW (State.sregs[5])
394 /* compare cccc field against PSW */
  /src/external/gpl3/gdb.old/dist/sim/v850/
v850-sim.h 25 reg_t sregs[32]; /* system registers, including psw */
110 #define PSW (State.sregs[5])
394 /* compare cccc field against PSW */

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