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      1 /*	$NetBSD: st-pincfg.h,v 1.1.1.2 2017/11/30 19:40:50 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 #ifndef _ST_PINCFG_H_
      5 #define _ST_PINCFG_H_
      6 
      7 /* Alternate functions */
      8 #define ALT1	1
      9 #define ALT2	2
     10 #define ALT3	3
     11 #define ALT4	4
     12 #define ALT5	5
     13 #define ALT6	6
     14 #define ALT7	7
     15 
     16 /* Output enable */
     17 #define OE			(1 << 27)
     18 /* Pull Up */
     19 #define PU			(1 << 26)
     20 /* Open Drain */
     21 #define OD			(1 << 25)
     22 #define RT			(1 << 23)
     23 #define INVERTCLK		(1 << 22)
     24 #define CLKNOTDATA		(1 << 21)
     25 #define DOUBLE_EDGE		(1 << 20)
     26 #define CLK_A			(0 << 18)
     27 #define CLK_B			(1 << 18)
     28 #define CLK_C			(2 << 18)
     29 #define CLK_D			(3 << 18)
     30 
     31 /* User-frendly defines for Pin Direction */
     32 		/* oe = 0, pu = 0, od = 0 */
     33 #define IN			(0)
     34 		/* oe = 0, pu = 1, od = 0 */
     35 #define IN_PU			(PU)
     36 		/* oe = 1, pu = 0, od = 0 */
     37 #define OUT			(OE)
     38 		/* oe = 1, pu = 0, od = 1 */
     39 #define BIDIR			(OE | OD)
     40 		/* oe = 1, pu = 1, od = 1 */
     41 #define BIDIR_PU		(OE | PU | OD)
     42 
     43 /* RETIME_TYPE */
     44 /*
     45  * B Mode
     46  * Bypass retime with optional delay parameter
     47  */
     48 #define BYPASS		(0)
     49 /*
     50  * R0, R1, R0D, R1D modes
     51  * single-edge data non inverted clock, retime data with clk
     52  */
     53 #define SE_NICLK_IO	(RT)
     54 /*
     55  * RIV0, RIV1, RIV0D, RIV1D modes
     56  * single-edge data inverted clock, retime data with clk
     57  */
     58 #define SE_ICLK_IO	(RT | INVERTCLK)
     59 /*
     60  * R0E, R1E, R0ED, R1ED modes
     61  * double-edge data, retime data with clk
     62  */
     63 #define DE_IO		(RT | DOUBLE_EDGE)
     64 /*
     65  * CIV0, CIV1 modes with inverted clock
     66  * Retiming the clk pins will park clock & reduce the noise within the core.
     67  */
     68 #define ICLK		(RT | CLKNOTDATA | INVERTCLK)
     69 /*
     70  * CLK0, CLK1 modes with non-inverted clock
     71  * Retiming the clk pins will park clock & reduce the noise within the core.
     72  */
     73 #define NICLK		(RT | CLKNOTDATA)
     74 #endif /* _ST_PINCFG_H_ */
     75