1 /* $NetBSD: marvell,pxa1928.h,v 1.1.1.2 2017/11/30 19:40:51 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 #ifndef __DTS_MARVELL_PXA1928_CLOCK_H 5 #define __DTS_MARVELL_PXA1928_CLOCK_H 6 7 /* 8 * Clock ID values here correspond to the control register offset/4. 9 */ 10 11 /* apb peripherals */ 12 #define PXA1928_CLK_RTC 0x00 13 #define PXA1928_CLK_TWSI0 0x01 14 #define PXA1928_CLK_TWSI1 0x02 15 #define PXA1928_CLK_TWSI2 0x03 16 #define PXA1928_CLK_TWSI3 0x04 17 #define PXA1928_CLK_OWIRE 0x05 18 #define PXA1928_CLK_KPC 0x06 19 #define PXA1928_CLK_TB_ROTARY 0x07 20 #define PXA1928_CLK_SW_JTAG 0x08 21 #define PXA1928_CLK_TIMER1 0x09 22 #define PXA1928_CLK_UART0 0x0b 23 #define PXA1928_CLK_UART1 0x0c 24 #define PXA1928_CLK_UART2 0x0d 25 #define PXA1928_CLK_GPIO 0x0e 26 #define PXA1928_CLK_PWM0 0x0f 27 #define PXA1928_CLK_PWM1 0x10 28 #define PXA1928_CLK_PWM2 0x11 29 #define PXA1928_CLK_PWM3 0x12 30 #define PXA1928_CLK_SSP0 0x13 31 #define PXA1928_CLK_SSP1 0x14 32 #define PXA1928_CLK_SSP2 0x15 33 34 #define PXA1928_CLK_TWSI4 0x1f 35 #define PXA1928_CLK_TWSI5 0x20 36 #define PXA1928_CLK_UART3 0x22 37 #define PXA1928_CLK_THSENS_GLOB 0x24 38 #define PXA1928_CLK_THSENS_CPU 0x26 39 #define PXA1928_CLK_THSENS_VPU 0x27 40 #define PXA1928_CLK_THSENS_GC 0x28 41 #define PXA1928_APBC_NR_CLKS 0x30 42 43 44 /* axi peripherals */ 45 #define PXA1928_CLK_SDH0 0x15 46 #define PXA1928_CLK_SDH1 0x16 47 #define PXA1928_CLK_USB 0x17 48 #define PXA1928_CLK_NAND 0x18 49 #define PXA1928_CLK_DMA 0x19 50 51 #define PXA1928_CLK_SDH2 0x3a 52 #define PXA1928_CLK_SDH3 0x3b 53 #define PXA1928_CLK_HSIC 0x3e 54 #define PXA1928_CLK_SDH4 0x57 55 #define PXA1928_CLK_GC3D 0x5d 56 #define PXA1928_CLK_GC2D 0x5f 57 58 #define PXA1928_APMU_NR_CLKS 0x60 59 60 #endif 61
Indexes created Mon Oct 06 08:10:01 GMT 2025