1 /* $NetBSD: r128fbreg.h,v 1.5 2012/01/06 13:59:50 macallan Exp $ */ 2 3 /* 4 * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario, 5 * Precision Insight, Inc., Cedar Park, Texas, and 6 * VA Linux Systems Inc., Fremont, California. 7 * 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining 11 * a copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation on the rights to use, copy, modify, merge, 14 * publish, distribute, sublicense, and/or sell copies of the Software, 15 * and to permit persons to whom the Software is furnished to do so, 16 * subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial 20 * portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 25 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX 26 * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 /* 33 * Authors: 34 * Rickard E. Faith <faith (at) valinux.com> 35 * Kevin E. Martin <martin (at) valinux.com> 36 * Gareth Hughes <gareth (at) valinux.com> 37 * 38 * References: 39 * 40 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 41 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 42 * 1999. 43 * 44 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 45 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 46 * 47 */ 48 49 /* 50 * register definitions for ATI Rage 128 graphics controllers 51 * mostly from XFree86's ati driver 52 */ 53 54 55 #ifndef R128FB_REG_H 56 #define R128FB_REG_H 57 58 /* RAMDAC */ 59 #define R128_PALETTE_DATA 0x00b4 60 #define R128_PALETTE_INDEX 0x00b0 61 62 /* flat panel registers */ 63 #define R128_FP_PANEL_CNTL 0x0288 64 #define FPCNT_DIGON 0x00000001 /* FP dig. voltage */ 65 #define FPCNT_BACKLIGHT_ON 0x00000002 66 #define FPCNT_BL_MODULATION_ON 0x00000004 67 #define FPCNT_BL_CLK_SEL 0x00000008 /* 1 - divide by 3 */ 68 #define FPCNT_MONID_EN 0x00000010 /* use MONID pins for 69 backlight control */ 70 #define FPCNT_FPENABLE_POL 0x00000020 /* 1 - active low */ 71 #define FPCNT_LEVEL_MASK 0x0000ff00 72 #define FPCNT_LEVEL_SHIFT 8 73 74 #define R128_LVDS_GEN_CNTL 0x02d0 75 # define R128_LVDS_ON (1 << 0) 76 # define R128_LVDS_DISPLAY_DIS (1 << 1) 77 # define R128_LVDS_EN (1 << 7) 78 # define R128_LVDS_DIGON (1 << 18) 79 # define R128_LVDS_BLON (1 << 19) 80 # define R128_LVDS_SEL_CRTC2 (1 << 23) 81 # define R128_HSYNC_DELAY_SHIFT 28 82 # define R128_HSYNC_DELAY_MASK (0xf << 28) 83 # define R128_LEVEL_MASK 0x0000ff00 84 # define R128_LEVEL_SHIFT 8 85 86 /* drawing engine */ 87 #define R128_PC_NGUI_CTLSTAT 0x0184 88 # define R128_PC_FLUSH_GUI (3 << 0) 89 # define R128_PC_RI_GUI (1 << 2) 90 # define R128_PC_FLUSH_ALL 0x00ff 91 # define R128_PC_BUSY (1 << 31) 92 93 #define R128_CRTC_OFFSET 0x0224 94 95 #define R128_DST_OFFSET 0x1404 96 #define R128_DST_PITCH 0x1408 97 98 #define R128_DP_GUI_MASTER_CNTL 0x146c 99 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 100 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 101 # define R128_GMC_SRC_CLIPPING (1 << 2) 102 # define R128_GMC_DST_CLIPPING (1 << 3) 103 # define R128_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 104 # define R128_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 105 # define R128_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 106 # define R128_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 107 # define R128_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 108 # define R128_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 109 # define R128_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 110 # define R128_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 111 # define R128_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 112 # define R128_GMC_BRUSH_8x8_COLOR (10 << 4) 113 # define R128_GMC_BRUSH_1X8_COLOR (12 << 4) 114 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 115 # define R128_GMC_BRUSH_NONE (15 << 4) 116 # define R128_GMC_DST_8BPP_CI (2 << 8) 117 # define R128_GMC_DST_15BPP (3 << 8) 118 # define R128_GMC_DST_16BPP (4 << 8) 119 # define R128_GMC_DST_24BPP (5 << 8) 120 # define R128_GMC_DST_32BPP (6 << 8) 121 # define R128_GMC_DST_8BPP_RGB (7 << 8) 122 # define R128_GMC_DST_Y8 (8 << 8) 123 # define R128_GMC_DST_RGB8 (9 << 8) 124 # define R128_GMC_DST_VYUY (11 << 8) 125 # define R128_GMC_DST_YVYU (12 << 8) 126 # define R128_GMC_DST_AYUV444 (14 << 8) 127 # define R128_GMC_DST_ARGB4444 (15 << 8) 128 # define R128_GMC_DST_DATATYPE_MASK (0x0f << 8) 129 # define R128_GMC_DST_DATATYPE_SHIFT 8 130 # define R128_GMC_SRC_DATATYPE_MASK (3 << 12) 131 # define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 132 # define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 133 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 134 # define R128_GMC_BYTE_PIX_ORDER (1 << 14) 135 # define R128_GMC_BYTE_MSB_TO_LSB (0 << 14) 136 # define R128_GMC_BYTE_LSB_TO_MSB (1 << 14) 137 # define R128_GMC_CONVERSION_TEMP (1 << 15) 138 # define R128_GMC_CONVERSION_TEMP_6500 (0 << 15) 139 # define R128_GMC_CONVERSION_TEMP_9300 (1 << 15) 140 # define R128_GMC_ROP3_MASK (0xff << 16) 141 # define R128_DP_SRC_SOURCE_MASK (7 << 24) 142 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 143 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 144 # define R128_DP_SRC_SOURCE_HOST_ALIGN (4 << 24) 145 # define R128_GMC_3D_FCN_EN (1 << 27) 146 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 147 # define R128_GMC_AUX_CLIP_DIS (1 << 29) 148 # define R128_GMC_WR_MSK_DIS (1 << 30) 149 # define R128_GMC_LD_BRUSH_Y_X (1 << 31) 150 # define R128_ROP3_ZERO 0x00000000 151 # define R128_ROP3_DSa 0x00880000 152 # define R128_ROP3_SDna 0x00440000 153 # define R128_ROP3_S 0x00cc0000 154 # define R128_ROP3_DSna 0x00220000 155 # define R128_ROP3_D 0x00aa0000 156 # define R128_ROP3_DSx 0x00660000 157 # define R128_ROP3_DSo 0x00ee0000 158 # define R128_ROP3_DSon 0x00110000 159 # define R128_ROP3_DSxn 0x00990000 160 # define R128_ROP3_Dn 0x00550000 161 # define R128_ROP3_SDno 0x00dd0000 162 # define R128_ROP3_Sn 0x00330000 163 # define R128_ROP3_DSno 0x00bb0000 164 # define R128_ROP3_DSan 0x00770000 165 # define R128_ROP3_ONE 0x00ff0000 166 # define R128_ROP3_DPa 0x00a00000 167 # define R128_ROP3_PDna 0x00500000 168 # define R128_ROP3_P 0x00f00000 169 # define R128_ROP3_DPna 0x000a0000 170 # define R128_ROP3_D 0x00aa0000 171 # define R128_ROP3_DPx 0x005a0000 172 # define R128_ROP3_DPo 0x00fa0000 173 # define R128_ROP3_DPon 0x00050000 174 # define R128_ROP3_PDxn 0x00a50000 175 # define R128_ROP3_PDno 0x00f50000 176 # define R128_ROP3_Pn 0x000f0000 177 # define R128_ROP3_DPno 0x00af0000 178 # define R128_ROP3_DPan 0x005f0000 179 180 #define R128_DP_BRUSH_BKGD_CLR 0x1478 181 #define R128_DP_BRUSH_FRGD_CLR 0x147c 182 #define R128_SRC_X_Y 0x1590 183 #define R128_DST_X_Y 0x1594 184 #define R128_DST_WIDTH_HEIGHT 0x1598 185 186 #define R128_SRC_OFFSET 0x15ac 187 #define R128_SRC_PITCH 0x15b0 188 189 #define R128_AUX_SC_CNTL 0x1660 190 # define R128_AUX1_SC_EN (1 << 0) 191 # define R128_AUX1_SC_MODE_OR (0 << 1) 192 # define R128_AUX1_SC_MODE_NAND (1 << 1) 193 # define R128_AUX2_SC_EN (1 << 2) 194 # define R128_AUX2_SC_MODE_OR (0 << 3) 195 # define R128_AUX2_SC_MODE_NAND (1 << 3) 196 # define R128_AUX3_SC_EN (1 << 4) 197 # define R128_AUX3_SC_MODE_OR (0 << 5) 198 # define R128_AUX3_SC_MODE_NAND (1 << 5) 199 200 #define R128_DP_CNTL 0x16c0 201 # define R128_DST_X_LEFT_TO_RIGHT (1 << 0) 202 # define R128_DST_Y_TOP_TO_BOTTOM (1 << 1) 203 204 #define R128_DP_DATATYPE 0x16c4 205 # define R128_HOST_BIG_ENDIAN_EN (1 << 29) 206 207 #define R128_DP_MIX 0x16c8 208 # define R128_MIX_SRC_VRAM (2 << 8) 209 # define R128_MIX_SRC_HOSTDATA (3 << 8) 210 # define R128_MIX_SRC_HOST_BYTEALIGN (4 << 8) 211 # define R128_MIX_SRC_ROP3_MASK (0xff << 16) 212 213 #define R128_DP_WRITE_MASK 0x16cc 214 #define R128_DP_SRC_BKGD_CLR 0x15dc 215 #define R128_DP_SRC_FRGD_CLR 0x15d8 216 217 #define R128_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 218 # define R128_DST_Y_MAJOR (1 << 2) 219 # define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 220 # define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 221 222 #define R128_DEFAULT_OFFSET 0x16e0 223 #define R128_DEFAULT_PITCH 0x16e4 224 #define R128_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 225 # define R128_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 226 # define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 227 228 /* scissor registers */ 229 #define R128_SC_BOTTOM 0x164c 230 #define R128_SC_BOTTOM_RIGHT 0x16f0 231 #define R128_SC_BOTTOM_RIGHT_C 0x1c8c 232 #define R128_SC_LEFT 0x1640 233 #define R128_SC_RIGHT 0x1644 234 #define R128_SC_TOP 0x1648 235 #define R128_SC_TOP_LEFT 0x16ec 236 #define R128_SC_TOP_LEFT_C 0x1c88 237 238 #define R128_GUI_STAT 0x1740 239 # define R128_GUI_FIFOCNT_MASK 0x0fff 240 # define R128_GUI_ACTIVE (1 << 31) 241 242 #define R128_HOST_DATA0 0x17c0 243 #define R128_HOST_DATA1 0x17c4 244 #define R128_HOST_DATA2 0x17c8 245 #define R128_HOST_DATA3 0x17cc 246 #define R128_HOST_DATA4 0x17d0 247 #define R128_HOST_DATA5 0x17d4 248 #define R128_HOST_DATA6 0x17d8 249 #define R128_HOST_DATA7 0x17dc 250 251 /* Information the firmware is supposed to leave for us */ 252 #define R128_BIOS_5_SCRATCH 0x0024 253 # define R128_BIOS_DISPLAY_FP (1 << 0) 254 # define R128_BIOS_DISPLAY_CRT (2 << 0) 255 # define R128_BIOS_DISPLAY_FP_CRT (3 << 0) 256 257 /* Clock stuff */ 258 #define R128_CLOCK_CNTL_INDEX 0x0008 259 # define R128_PLL_WR_EN (1 << 7) 260 # define R128_PLL_DIV_SEL (3 << 8) 261 # define R128_PLL2_DIV_SEL_MASK ~(3 << 8) 262 #define R128_CLOCK_CNTL_DATA 0x000c 263 264 #define R128_CLK_PIN_CNTL 0x0001 /* PLL */ 265 #define R128_PPLL_CNTL 0x0002 /* PLL */ 266 # define R128_PPLL_RESET (1 << 0) 267 # define R128_PPLL_SLEEP (1 << 1) 268 # define R128_PPLL_ATOMIC_UPDATE_EN (1 << 16) 269 # define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 270 #define R128_PPLL_REF_DIV 0x0003 /* PLL */ 271 # define R128_PPLL_REF_DIV_MASK 0x03ff 272 # define R128_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 273 # define R128_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 274 #define R128_PPLL_DIV_0 0x0004 /* PLL */ 275 #define R128_PPLL_DIV_1 0x0005 /* PLL */ 276 #define R128_PPLL_DIV_2 0x0006 /* PLL */ 277 #define R128_PPLL_DIV_3 0x0007 /* PLL */ 278 # define R128_PPLL_FB3_DIV_MASK 0x07ff 279 # define R128_PPLL_POST3_DIV_MASK 0x00070000 280 #define R128_VCLK_ECP_CNTL 0x0008 /* PLL */ 281 # define R128_VCLK_SRC_SEL_MASK 0x03 282 # define R128_VCLK_SRC_SEL_CPUCLK 0x00 283 # define R128_VCLK_SRC_SEL_PPLLCLK 0x03 284 # define R128_ECP_DIV_MASK (3 << 8) 285 #define R128_HTOTAL_CNTL 0x0009 /* PLL */ 286 #define R128_X_MPLL_REF_FB_DIV 0x000a /* PLL */ 287 #define R128_XPLL_CNTL 0x000b /* PLL */ 288 #define R128_XDLL_CNTL 0x000c /* PLL */ 289 #define R128_XCLK_CNTL 0x000d /* PLL */ 290 #define R128_FCP_CNTL 0x0012 /* PLL */ 291 292 #define R128_P2PLL_CNTL 0x002a /* P2PLL */ 293 # define R128_P2PLL_RESET (1 << 0) 294 # define R128_P2PLL_SLEEP (1 << 1) 295 # define R128_P2PLL_ATOMIC_UPDATE_EN (1 << 16) 296 # define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 297 # define R128_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 298 #define R128_P2PLL_REF_DIV 0x002B /* PLL */ 299 # define R128_P2PLL_REF_DIV_MASK 0x03ff 300 # define R128_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 301 # define R128_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 302 #define R128_P2PLL_DIV_0 0x002c 303 # define R128_P2PLL_FB0_DIV_MASK 0x07ff 304 # define R128_P2PLL_POST0_DIV_MASK 0x00070000 305 #define R128_V2CLK_VCLKTV_CNTL 0x002d /* PLL */ 306 # define R128_V2CLK_SRC_SEL_MASK 0x03 307 # define R128_V2CLK_SRC_SEL_CPUCLK 0x00 308 # define R128_V2CLK_SRC_SEL_P2PLLCLK 0x03 309 #define R128_HTOTAL2_CNTL 0x002e /* PLL */ 310 311 /* CTRCs */ 312 #define R128_CRTC_GEN_CNTL 0x0050 313 # define R128_CRTC_DBL_SCAN_EN (1 << 0) 314 # define R128_CRTC_INTERLACE_EN (1 << 1) 315 # define R128_CRTC_CSYNC_EN (1 << 4) 316 # define R128_CRTC_PIX_WIDTH (7 << 8) 317 # define R128_CRTC_COLOR_8BIT (2 << 8) 318 # define R128_CRTC_COLOR_15BIT (3 << 8) 319 # define R128_CRTC_COLOR_16BIT (4 << 8) 320 # define R128_CRTC_COLOR_24BIT (5 << 8) 321 # define R128_CRTC_COLOR_32BIT (6 << 8) 322 # define R128_CRTC_CUR_EN (1 << 16) 323 # define R128_CRTC_CUR_MODE_MASK (7 << 17) 324 # define R128_CRTC_ICON_EN (1 << 20) 325 # define R128_CRTC_EXT_DISP_EN (1 << 24) 326 # define R128_CRTC_EN (1 << 25) 327 # define R128_CRTC_DISP_REQ_EN_B (1 << 26) 328 #define R128_CRTC_EXT_CNTL 0x0054 329 # define R128_CRTC_VGA_XOVERSCAN (1 << 0) 330 # define R128_VGA_ATI_LINEAR (1 << 3) 331 # define R128_XCRT_CNT_EN (1 << 6) 332 # define R128_CRTC_HSYNC_DIS (1 << 8) 333 # define R128_CRTC_VSYNC_DIS (1 << 9) 334 # define R128_CRTC_DISPLAY_DIS (1 << 10) 335 # define R128_CRTC_CRT_ON (1 << 15) 336 # define R128_FP_OUT_EN (1 << 22) 337 # define R128_FP_ACTIVE (1 << 23) 338 #define R128_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 339 # define R128_CRTC_HSYNC_DIS_BYTE (1 << 0) 340 # define R128_CRTC_VSYNC_DIS_BYTE (1 << 1) 341 # define R128_CRTC_DISPLAY_DIS_BYTE (1 << 2) 342 #define R128_CRTC_STATUS 0x005c 343 # define R128_CRTC_VBLANK_SAVE (1 << 1) 344 345 #define R128_CRTC_H_TOTAL_DISP 0x0200 346 # define R128_CRTC_H_TOTAL (0x01ff << 0) 347 # define R128_CRTC_H_TOTAL_SHIFT 0 348 # define R128_CRTC_H_DISP (0x00ff << 16) 349 # define R128_CRTC_H_DISP_SHIFT 16 350 #define R128_CRTC_H_SYNC_STRT_WID 0x0204 351 # define R128_CRTC_H_SYNC_STRT_PIX (0x07 << 0) 352 # define R128_CRTC_H_SYNC_STRT_CHAR (0x1ff << 3) 353 # define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 354 # define R128_CRTC_H_SYNC_WID (0x3f << 16) 355 # define R128_CRTC_H_SYNC_WID_SHIFT 16 356 # define R128_CRTC_H_SYNC_POL (1 << 23) 357 #define R128_CRTC_V_TOTAL_DISP 0x0208 358 # define R128_CRTC_V_TOTAL (0x07ff << 0) 359 # define R128_CRTC_V_TOTAL_SHIFT 0 360 # define R128_CRTC_V_DISP (0x07ff << 16) 361 # define R128_CRTC_V_DISP_SHIFT 16 362 #define R128_CRTC_V_SYNC_STRT_WID 0x020c 363 # define R128_CRTC_V_SYNC_STRT (0x7ff << 0) 364 # define R128_CRTC_V_SYNC_STRT_SHIFT 0 365 # define R128_CRTC_V_SYNC_WID (0x1f << 16) 366 # define R128_CRTC_V_SYNC_WID_SHIFT 16 367 # define R128_CRTC_V_SYNC_POL (1 << 23) 368 #define R128_CRTC_VLINE_CRNT_VLINE 0x0210 369 # define R128_CRTC_CRNT_VLINE_MASK (0x7ff << 16) 370 #define R128_CRTC_CRNT_FRAME 0x0214 371 #define R128_CRTC_GUI_TRIG_VLINE 0x0218 372 #define R128_CRTC_DEBUG 0x021c 373 #define R128_CRTC_OFFSET 0x0224 374 #define R128_CRTC_OFFSET_CNTL 0x0228 375 #define R128_CRTC_PITCH 0x022c 376 377 #define R128_CRTC2_H_TOTAL_DISP 0x0300 378 # define R128_CRTC2_H_TOTAL (0x01ff << 0) 379 # define R128_CRTC2_H_TOTAL_SHIFT 0 380 # define R128_CRTC2_H_DISP (0x00ff << 16) 381 # define R128_CRTC2_H_DISP_SHIFT 16 382 #define R128_CRTC2_H_SYNC_STRT_WID 0x0304 383 # define R128_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) 384 # define R128_CRTC2_H_SYNC_STRT_CHAR (0x1ff << 3) 385 # define R128_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 386 # define R128_CRTC2_H_SYNC_WID (0x3f << 16) 387 # define R128_CRTC2_H_SYNC_WID_SHIFT 16 388 # define R128_CRTC2_H_SYNC_POL (1 << 23) 389 #define R128_CRTC2_V_TOTAL_DISP 0x0308 390 # define R128_CRTC2_V_TOTAL (0x07ff << 0) 391 # define R128_CRTC2_V_TOTAL_SHIFT 0 392 # define R128_CRTC2_V_DISP (0x07ff << 16) 393 # define R128_CRTC2_V_DISP_SHIFT 16 394 #define R128_CRTC2_V_SYNC_STRT_WID 0x030c 395 # define R128_CRTC2_V_SYNC_STRT (0x7ff << 0) 396 # define R128_CRTC2_V_SYNC_STRT_SHIFT 0 397 # define R128_CRTC2_V_SYNC_WID (0x1f << 16) 398 # define R128_CRTC2_V_SYNC_WID_SHIFT 16 399 # define R128_CRTC2_V_SYNC_POL (1 << 23) 400 #define R128_CRTC2_VLINE_CRNT_VLINE 0x0310 401 #define R128_CRTC2_CRNT_FRAME 0x0314 402 #define R128_CRTC2_GUI_TRIG_VLINE 0x0318 403 #define R128_CRTC2_DEBUG 0x031c 404 #define R128_CRTC2_OFFSET 0x0324 405 #define R128_CRTC2_OFFSET_CNTL 0x0328 406 # define R128_CRTC2_TILE_EN (1 << 15) 407 #define R128_CRTC2_PITCH 0x032c 408 #define R128_CRTC2_GEN_CNTL 0x03f8 409 # define R128_CRTC2_DBL_SCAN_EN (1 << 0) 410 # define R128_CRTC2_CUR_EN (1 << 16) 411 # define R128_CRTC2_ICON_EN (1 << 20) 412 # define R128_CRTC2_DISP_DIS (1 << 23) 413 # define R128_CRTC2_EN (1 << 25) 414 # define R128_CRTC2_DISP_REQ_EN_B (1 << 26) 415 #define R128_CRTC2_STATUS 0x03fc 416 417 #endif /* R128FB_REG_H */ 418
Indexes created Tue Sep 30 20:09:53 GMT 2025