HomeSort by: relevance | last modified time | path
    Searched defs:RCID (Results 1 - 8 of 8) sorted by relevancy

  /src/crypto/external/apache2/openssl/dist/ssl/quic/
quic_rcidm.c 21 * to switch to a new RCID according to some arbitrary policy such as the number
24 * When we do this we should move to the next RCID in the sequence of received
31 * with sequence numbers 12, 10, 11, we should still consume the RCID with
38 const QUIC_CONN_ID *rcid);
46 * RCID
49 * The RCID structure is used to track RCIDs which have sequence numbers (i.e.,
52 * can logically be viewed as their own type of RCID but are tracked separately
55 * At any given time an RCID object is in one of these states:
73 * The RCID object is freed when it is popped.
77 * rcid->state == RCID_STATE_PENDING
305 RCID *rcid, *rnext; local
346 RCID *rcid; local
444 RCID *rcid; local
474 RCID *rcid; local
492 RCID *rcid; local
614 RCID *rcid; local
632 RCID *rcid = ossl_list_retiring_head(&rcidm->retiring_list); local
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineInstr.cpp 905 unsigned RCID;
909 InlineAsm::hasRegClassConstraint(Flag, RCID))
910 return TRI->getRegClass(RCID);
1748 unsigned RCID = 0;
1750 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1752 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1754 OS << ":RC" << RCID;
TargetInstrInfo.cpp 1398 unsigned RCID = 0;
1400 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1402 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1404 OS << ":RC" << RCID;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FloatingPoint.cpp 1532 unsigned RCID;
1550 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUInstPrinter.cpp 679 int RCID = Desc.OpInfo[OpNo].RegClass;
680 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 584 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
586 Subtarget->getRegisterInfo()->getRegClass(RCID);
SIInstrInfo.cpp 4434 unsigned RCID,
4439 switch (RCID) {
4449 return RCID;
4497 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
4498 RCID = adjustAllocatableRegClass(ST, MRI, Desc, RCID, true);
4499 return RI.getRegClass(RCID);
4507 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
4508 const TargetRegisterClass *RC = RI.getRegClass(RCID);
7379 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 249 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {
250 return isRegClass(RCID) || isInlinableImm(type) || isLiteralImm(type);
370 bool isRegClass(unsigned RCID) const;
374 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {
375 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers();
1897 bool AMDGPUOperand::isRegClass(unsigned RCID) const {
1898 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
2453 int RCID = getRegClass(RegKind, RegWidth);
2454 if (RCID == -1) {
2460 const MCRegisterClass RC = TRI->getRegClass(RCID);
    [all...]

Completed in 124 milliseconds