| /src/sys/arch/arm/ti/ |
| ti_omapmusb.c | 79 #define RD2(sc, reg) \
99 inttx = RD2(sc, MUSB2_REG_INTTX);
100 intrx = RD2(sc, MUSB2_REG_INTRX);
|
| /src/sys/arch/evbppc/nintendo/dev/ |
| avenc.c | 58 #define RD2 avenc_read_2
143 val = RD2(avenc_tag, avenc_addr, AVENC_VOLUME);
|
| wiifb.c | 156 #define RD2(sc, reg) \
699 dcr = RD2(sc, VI_DCR);
704 visel = RD2(sc, VI_VISEL);
813 WR2(sc, VI_DCR, RD2(sc, VI_DCR) | VI_DCR_ENB);
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| m10300-opc.c | 283 #define RD2 (RD0+1)
288 #define IMM8_MEM (RD2+1)
523 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
530 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
591 { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
596 { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
601 { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
606 { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
611 { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
616 { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| m10300-opc.c | 283 #define RD2 (RD0+1)
288 #define IMM8_MEM (RD2+1)
523 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
530 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
591 { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
596 { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
601 { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
606 { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
611 { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
616 { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| m10300-opc.c | 283 #define RD2 (RD0+1)
288 #define IMM8_MEM (RD2+1)
523 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
530 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
591 { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
596 { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
601 { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
606 { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
611 { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
616 { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| m10300-opc.c | 283 #define RD2 (RD0+1)
288 #define IMM8_MEM (RD2+1)
523 { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
530 { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
591 { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
596 { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
601 { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
606 { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
611 { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
616 { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}}
[all...] |
| /src/external/gpl3/gcc/dist/libquadmath/math/ |
| lgammaq.c | 541 static const __float128 RD2[NRD2 + 1] =
851 p = z * neval (z, RN2, NRN2) / deval (z, RD2, NRD2);
879 p = z * neval (z, RN2, NRN2) / deval (z, RD2, NRD2);
936 p = z * neval (z, RN2, NRN2) / deval (z, RD2, NRD2);
|
| /src/external/gpl3/gcc.old/dist/libquadmath/math/ |
| lgammaq.c | 541 static const __float128 RD2[NRD2 + 1] =
851 p = z * neval (z, RN2, NRN2) / deval (z, RD2, NRD2);
879 p = z * neval (z, RN2, NRN2) / deval (z, RD2, NRD2);
936 p = z * neval (z, RN2, NRN2) / deval (z, RD2, NRD2);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 3101 // li $rd2, 1
3103 // $rd = phi($rd1, $fbb, $rd2, $tbb)
3142 Register RD2 = RegInfo.createVirtualRegister(RC);
3143 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3151 .addReg(RD2)
|
| /src/external/bsd/pcc/dist/pcc/arch/hppa/ |
| macdefs.h | 153 #define RD2 34 /* r1:t4 */
320 { RD1, RD2, RD3, RD4, RD5, -1 },\
|
