Searched defs:REG (Results 1 - 25 of 86) sorted by relevance

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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
H A D	rv1_clk_mgr_clk.c	52 #define REG(reg_name) \ macro
H A D	amdgpu_rv1_clk_mgr_vbios_smu.c	67 #define REG(reg_name) \ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A D	amdgpu_dcn20_vmid.c	36 #define REG(reg)\ macro
H A D	amdgpu_dcn20_dccg.c	40 #define REG(reg) \ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
H A D	amdgpu_bios_parser_helper.c	55 #define REG(reg)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A D	amdgpu_dcn10_ipp.c	37 #define REG(reg) \ macro
H A D	dcn10_dwb.c	39 #define REG(reg)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
H A D	amdgpu_hw_translate_dce120.c	56 #define REG(reg_name)\ macro [all...]
H A D	amdgpu_hw_factory_dce120.c	65 #define REG(reg_name)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
H A D	amdgpu_hw_translate_dcn10.c	56 #define REG(reg_name)\ macro [all...]
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A D	amdgpu_dce120_hw_sequencer.c	47 #define REG(reg)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A D	amdgpu_dcn21_hwseq.c	46 #define REG(reg)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
H A D	amdgpu_hw_generic.c	49 #define REG(reg)\ macro
H A D	amdgpu_hw_ddc.c	51 #define REG(reg)\ macro
H A D	amdgpu_hw_gpio.c	44 #define REG(reg)\ macro
H A D	amdgpu_hw_hpd.c	49 #define REG(reg)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/
H A D	amdgpu_hw_factory_dce110.c	50 #define REG(reg_name)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/
H A D	amdgpu_hw_factory_dce80.c	46 #define REG(reg_name)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
H A D	amdgpu_hw_translate_dcn20.c	60 #define REG(reg_name)\ macro [all...]
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
H A D	amdgpu_hw_translate_dcn21.c	60 #define REG(reg_name)\ macro [all...]
/src/sys/arch/ia64/disasm/
H A D	disasm_int.h	63 #define REG(i,r) FIELD(i, ((r) - 1) * REG_BITS + QP_BITS, REG_BITS) macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A D	amdgpu_dce_ipp.c	37 #define REG(reg) \ macro
H A D	amdgpu_dce_hwseq.c	38 #define REG(reg)\ macro
H A D	amdgpu_dce_opp.c	40 #define REG(reg)\ macro
/src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
H A D	dmub_reg.h	45 #define REG(reg) (REGS)->offset.reg macro

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Indexes created Tue Dec 02 23:09:33 GMT 2025