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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
rv1_clk_mgr_clk.c 52 #define REG(reg_name) \
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_ipp.c 37 #define REG(reg) \
38 (ippn10->regs->reg)
dcn10_dwb.c 39 #define REG(reg)\
40 dwbc10->dwbc_regs->reg
amdgpu_dcn10_opp.c 37 #define REG(reg) \
38 (oppn10->regs->reg)
382 if (REG(OPPBUF_CONTROL1))
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_vmid.c 36 #define REG(reg)\
37 vmid->regs->reg
amdgpu_dcn20_mmhubbub.c 38 #define REG(reg)\
39 mcif_wb20->mcif_wb_regs->reg
amdgpu_dcn20_dccg.c 40 #define REG(reg) \
41 (dccg_dcn->regs->reg)
amdgpu_dcn20_dwb.c 38 #define REG(reg)\
39 dwbc20->dwbc_regs->reg
amdgpu_dcn20_link_encoder.c 47 #define REG(reg)\
48 (enc10->link_regs->reg)
268 #define AUX_REG(reg)\
269 (enc10->aux_regs->reg)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
amdgpu_hw_translate_dce120.c 56 #define REG(reg_name)\
74 case REG(DC_GPIO_GENERIC_A):
104 case REG(DC_GPIO_HPD_A):
131 case REG(DC_GPIO_SYNCA_A):
145 /* REG(DC_GPIO_GENLK_MASK */
146 case REG(DC_GPIO_GENLK_A):
170 case REG(DC_GPIO_DDC1_A):
173 case REG(DC_GPIO_DDC2_A):
176 case REG(DC_GPIO_DDC3_A):
179 case REG(DC_GPIO_DDC4_A)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
amdgpu_hw_translate_dcn10.c 56 #define REG(reg_name)\
74 case REG(DC_GPIO_GENERIC_A):
104 case REG(DC_GPIO_HPD_A):
131 case REG(DC_GPIO_SYNCA_A):
145 /* REG(DC_GPIO_GENLK_MASK */
146 case REG(DC_GPIO_GENLK_A):
170 case REG(DC_GPIO_DDC1_A):
173 case REG(DC_GPIO_DDC2_A):
176 case REG(DC_GPIO_DDC3_A):
179 case REG(DC_GPIO_DDC4_A)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_bios_parser_helper.c 55 #define REG(reg)\
56 (bios->regs->reg)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_ipp.c 37 #define REG(reg) \
38 (ipp_dce->regs->reg)
184 if (REG(DCFE_MEM_PWR_CTRL))
216 if (REG(DCFE_MEM_PWR_CTRL))
amdgpu_dce_hwseq.c 38 #define REG(reg)\
39 hws->regs->reg
116 if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
136 if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
144 if (REG(DCFEV_CLOCK_CONTROL))
196 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
amdgpu_dce_opp.c 40 #define REG(reg)\
41 (opp110->regs->reg)
300 if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_hw_sequencer.c 47 #define REG(reg)\
48 hws->regs->reg
79 #define HW_REG_CRTC(reg, id)\
80 (reg + reg_offsets[id].crtc)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_hwseq.c 46 #define REG(reg)\
47 hws->regs->reg
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
amdgpu_hw_generic.c 49 #define REG(reg)\
50 (generic->regs->reg)
amdgpu_hw_gpio.c 44 #define REG(reg)\
45 (gpio->regs->reg)
amdgpu_hw_hpd.c 49 #define REG(reg)\
50 (hpd->regs->reg)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_translate_dcn20.c 59 #undef REG
60 #define REG(reg_name)\
78 case REG(DC_GPIO_GENERIC_A):
108 case REG(DC_GPIO_HPD_A):
134 /* REG(DC_GPIO_GENLK_MASK */
135 case REG(DC_GPIO_GENLK_A):
159 case REG(DC_GPIO_DDC1_A):
162 case REG(DC_GPIO_DDC2_A):
165 case REG(DC_GPIO_DDC3_A):
168 case REG(DC_GPIO_DDC4_A)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
amdgpu_hw_translate_dcn21.c 59 #undef REG
60 #define REG(reg_name)\
77 case REG(DC_GPIO_GENERIC_A):
111 case REG(DC_GPIO_HPD_A):
137 /* REG(DC_GPIO_GENLK_MASK */
138 case REG(DC_GPIO_GENLK_A):
162 case REG(DC_GPIO_DDC1_A):
165 case REG(DC_GPIO_DDC2_A):
168 case REG(DC_GPIO_DDC3_A):
171 case REG(DC_GPIO_DDC4_A)
    [all...]
  /src/sys/arch/ia64/disasm/
disasm_int.h 63 #define REG(i,r) FIELD(i, ((r) - 1) * REG_BITS + QP_BITS, REG_BITS)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce110/
amdgpu_hw_factory_dce110.c 50 #define REG(reg_name)\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce80/
amdgpu_hw_factory_dce80.c 46 #define REG(reg_name)\

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