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Searched defs:REGS (Results 1 - 6 of 6) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
amdgpu_dmub_dcn21.c	`41 #define REGS dmub->regs`
amdgpu_dmub_dcn20.c	`42 #define REGS dmub->regs`
/src/external/gpl3/binutils/dist/opcodes/
m10300-opc.c	`216 #define REGS (REGS_SHIFT8+1) 220 #define USP (REGS+1) 758 { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, 759 { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, 760 { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, 761 { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, 1012 { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},`
/src/external/gpl3/binutils.old/dist/opcodes/
m10300-opc.c	`216 #define REGS (REGS_SHIFT8+1) 220 #define USP (REGS+1) 758 { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, 759 { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, 760 { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, 761 { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, 1012 { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},`
/src/external/gpl3/gdb.old/dist/opcodes/
m10300-opc.c	`216 #define REGS (REGS_SHIFT8+1) 220 #define USP (REGS+1) 758 { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, 759 { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, 760 { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, 761 { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, 1012 { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},`
/src/external/gpl3/gdb/dist/opcodes/
m10300-opc.c	`216 #define REGS (REGS_SHIFT8+1) 220 #define USP (REGS+1) 758 { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}}, 759 { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}}, 760 { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}}, 761 { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}}, 1012 { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},`

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