HomeSort by: relevance | last modified time | path
    Searched defs:REG_READ (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/dev/goldfish/
gfpic.c 54 #define REG_READ(sc, r) \
106 return ffs(REG_READ(sc, GFPIC_PENDING)) - 1;
gftty.c 78 #define REG_READ(sc, r) REG_READ0((sc)->sc_config, (r))
311 while ((count = REG_READ(sc, GFTTY_BYTES_READY)) != 0) {
342 count = REG_READ(sc, GFTTY_BYTES_READY);
  /src/sys/arch/virt68k/dev/
virtctrl.c 64 #define REG_READ(sc, r) \
113 feat = REG_READ(sc, VIRTCTRL_REG_FEATURES);
  /src/sys/arch/mips/adm5120/
adm5120_intr.c 158 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o)))
159 #define REG_WRITE(o,v) (REG_READ(o)) = (v)
220 REG_READ(ICU_MODE_REG) | irqmask);
223 REG_READ(ICU_MODE_REG) & ~irqmask);
275 irqstat = REG_READ(ICU_FIQ_STATUS_REG);
277 irqstat = REG_READ(ICU_STATUS_REG);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
dmub_reg.h 53 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
  /src/sys/arch/mips/adm5120/dev/
uart.c 54 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o))
339 if (REG_READ(UART_RSR_REG) & UART_RSR_BE) {
344 while ((REG_READ(UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) == 0) {
345 c = REG_READ(UART_DR_REG) & 0xff;
if_admsw.c 164 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o))
254 REG_READ(PORT_CONF0_REG) | PORT_CONF0_DP_MASK);
256 REG_READ(CPUP_CONF_REG) | CPUP_CONF_DCPUP);
267 REG_READ(PHY_CNTL2_REG) & ~PHY_CNTL2_PHYR_MASK);
284 REG_READ(PHY_CNTL2_REG) | PHY_CNTL2_ANE_MASK |
287 REG_WRITE(PHY_CNTL3_REG, REG_READ(PHY_CNTL3_REG) | PHY_CNTL3_RNT);
302 REG_READ(FC_TH_REG) & ~(FC_TH_FCS_MASK | FC_TH_D2S_MASK));
316 while (!(REG_READ(MAC_WT0_REG) & MAC_WT0_WRITE_DONE))
319 wdog1 = REG_READ(ADM5120_WDOG1);
802 pending = REG_READ(ADMSW_INT_ST)
    [all...]
ahci.c 244 #define REG_READ(o) bus_space_read_4(sc->sc_st, sc->sc_ioh, (o))
294 while (REG_READ(ADMHCD_REG_CONTROL) & ADMHCD_SW_RESET)
464 if ((REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS) != p0_state) {
467 p0_state=(REG_READ(ADMHCD_REG_PORTSTATUS0) & ADMHCD_CCS);
469 if ((REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS) != p1_state) {
472 p1_state=(REG_READ(ADMHCD_REG_PORTSTATUS1) & ADMHCD_CCS);
677 status = REG_READ(ADMHCD_REG_PORTSTATUS0+(index-1)*4);
873 /* printf("status: %x\n",REG_READ(ADMHCD_REG_PORTSTATUS0));
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
reg_helper.h 41 #define REG_READ(reg_name) \
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312reg.h 32 #define REG_READ(_reg) *((volatile uint32_t *)(_reg))
  /src/sys/dev/pcmcia/
if_ray.c 386 #define REG_READ(sc, off) \
425 #define RAY_ECF_READY(sc) (!(REG_READ(sc, RAY_ECFIR) & RAY_ECSIR_IRQ))
2022 if (!REG_READ(sc, RAY_HCSIR))

Completed in 20 milliseconds