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      1 /* $NetBSD: meson_dwmac.c,v 1.16 2024/10/13 08:55:24 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     17  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  * POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 
     31 __KERNEL_RCSID(0, "$NetBSD: meson_dwmac.c,v 1.16 2024/10/13 08:55:24 skrll Exp $");
     32 
     33 #include <sys/param.h>
     34 #include <sys/bus.h>
     35 #include <sys/device.h>
     36 #include <sys/intr.h>
     37 #include <sys/systm.h>
     38 #include <sys/gpio.h>
     39 #include <sys/rndsource.h>
     40 
     41 #include <net/if.h>
     42 #include <net/if_ether.h>
     43 #include <net/if_media.h>
     44 
     45 #include <dev/mii/miivar.h>
     46 
     47 #include <dev/ic/dwc_gmac_var.h>
     48 #include <dev/ic/dwc_gmac_reg.h>
     49 
     50 #include <dev/fdt/fdtvar.h>
     51 
     52 #define	PRG_ETHERNET_ADDR0		0x00
     53 #define	 CLKGEN_ENABLE			__BIT(12)
     54 #define	 RMII_CLK_I_INVERTED		__BIT(11)
     55 #define	 PHY_CLK_ENABLE			__BIT(10)
     56 #define	 MP2_CLK_OUT_DIV		__BITS(9,7)
     57 #define	 TX_CLK_DELAY			__BITS(6,5)
     58 #define	 PHY_INTERFACE_SEL		__BIT(0)
     59 
     60 static const struct device_compatible_entry compat_data[] = {
     61 	{ .compat = "amlogic,meson8b-dwmac" },
     62 	{ .compat = "amlogic,meson-gx-dwmac" },
     63 	{ .compat = "amlogic,meson-gxbb-dwmac" },
     64 	{ .compat = "amlogic,meson-axg-dwmac" },
     65 	DEVICE_COMPAT_EOL
     66 };
     67 
     68 static int
     69 meson_dwmac_reset_eth(const int phandle)
     70 {
     71 	struct fdtbus_gpio_pin *pin_reset;
     72 	const u_int *reset_delay_us;
     73 	bool reset_active_low;
     74 	int len, val;
     75 
     76 	pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio",
     77 	    GPIO_PIN_OUTPUT);
     78 	if (pin_reset == NULL)
     79 		return ENXIO;
     80 
     81 	reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len);
     82 	if (reset_delay_us == NULL || len != 12)
     83 		return ENXIO;
     84 
     85 	reset_active_low = of_hasprop(phandle, "snps,reset-active-low");
     86 
     87 	val = reset_active_low ? 1 : 0;
     88 
     89 	fdtbus_gpio_write(pin_reset, val);
     90 	delay(be32toh(reset_delay_us[0]));
     91 	fdtbus_gpio_write(pin_reset, !val);
     92 	delay(be32toh(reset_delay_us[1]));
     93 	fdtbus_gpio_write(pin_reset, val);
     94 	delay(be32toh(reset_delay_us[2]));
     95 
     96 	return 0;
     97 }
     98 
     99 static int
    100 meson_dwmac_reset_phy(const int phandle)
    101 {
    102 	struct fdtbus_gpio_pin *pin_reset;
    103 	const u_int *reset_assert_us, *reset_deassert_us, *reset_gpios;
    104 	bool reset_active_low;
    105 	int len, val;
    106 
    107 	pin_reset = fdtbus_gpio_acquire(phandle, "reset-gpios",
    108 	    GPIO_PIN_OUTPUT);
    109 	if (pin_reset == NULL)
    110 		return ENXIO;
    111 
    112 	reset_assert_us = fdtbus_get_prop(phandle, "reset-assert-us", &len);
    113 	if (reset_assert_us == NULL || len != 4)
    114 		return ENXIO;
    115 	reset_deassert_us = fdtbus_get_prop(phandle, "reset-deassert-us", &len);
    116 	if (reset_deassert_us == NULL || len != 4)
    117 		return ENXIO;
    118 	reset_gpios = fdtbus_get_prop(phandle, "reset-gpios", &len);
    119 	if (reset_gpios == NULL || len != 12)
    120 		return ENXIO;
    121 
    122 	reset_active_low = be32toh(reset_gpios[2]);
    123 
    124 	val = reset_active_low ? 1 : 0;
    125 
    126 	fdtbus_gpio_write(pin_reset, val);
    127 	delay(be32toh(reset_assert_us[0]));
    128 	fdtbus_gpio_write(pin_reset, !val);
    129 	delay(be32toh(reset_deassert_us[0]));
    130 
    131 	return 0;
    132 }
    133 
    134 static void
    135 meson_dwmac_set_mode_rgmii(int phandle, bus_space_tag_t bst,
    136     bus_space_handle_t bsh, struct clk *clkin)
    137 {
    138 	u_int tx_delay;
    139 	uint32_t val;
    140 
    141 #define DIV_ROUND_OFF(x, y)	(((x) + (y) / 2) / (y))
    142 	const u_int div = DIV_ROUND_OFF(clk_get_rate(clkin), 250000000);
    143 
    144 	if (of_getprop_uint32(phandle, "amlogic,tx-delay-ns", &tx_delay) != 0)
    145 		tx_delay = 2;
    146 
    147 	val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0);
    148 	val |= PHY_INTERFACE_SEL;
    149 	val &= ~TX_CLK_DELAY;
    150 	val |= __SHIFTIN((tx_delay >> 1), TX_CLK_DELAY);
    151 	val &= ~MP2_CLK_OUT_DIV;
    152 	val |= __SHIFTIN(div, MP2_CLK_OUT_DIV);
    153 	val |= PHY_CLK_ENABLE;
    154 	val |= CLKGEN_ENABLE;
    155 	bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val);
    156 }
    157 
    158 static void
    159 meson_dwmac_set_mode_rmii(int phandle, bus_space_tag_t bst,
    160     bus_space_handle_t bsh)
    161 {
    162 	uint32_t val;
    163 
    164 	val = bus_space_read_4(bst, bsh, PRG_ETHERNET_ADDR0);
    165 	val &= ~PHY_INTERFACE_SEL;
    166 	val |= RMII_CLK_I_INVERTED;
    167 	val &= ~TX_CLK_DELAY;
    168 	val |= CLKGEN_ENABLE;
    169 	bus_space_write_4(bst, bsh, PRG_ETHERNET_ADDR0, val);
    170 }
    171 
    172 static int
    173 meson_dwmac_intr(void *arg)
    174 {
    175 	struct dwc_gmac_softc * const sc = arg;
    176 
    177 	return dwc_gmac_intr(sc);
    178 }
    179 
    180 static int
    181 meson_dwmac_match(device_t parent, cfdata_t cf, void *aux)
    182 {
    183 	struct fdt_attach_args * const faa = aux;
    184 
    185 	return of_compatible_match(faa->faa_phandle, compat_data);
    186 }
    187 
    188 static void
    189 meson_dwmac_attach(device_t parent, device_t self, void *aux)
    190 {
    191 	struct dwc_gmac_softc * const sc = device_private(self);
    192 	struct fdt_attach_args * const faa = aux;
    193 	const int phandle = faa->faa_phandle;
    194 	int miiclk, phandle_phy, phy = MII_PHY_ANY;
    195 	u_int miiclk_rate;
    196 	bus_space_handle_t prgeth_bsh;
    197 	struct fdtbus_reset *rst_gmac;
    198 	struct clk *clk_gmac, *clk_in[2];
    199 	const char *phy_mode;
    200 	char intrstr[128];
    201 	bus_addr_t addr[2];
    202 	bus_size_t size[2];
    203 
    204 	if (fdtbus_get_reg(phandle, 0, &addr[0], &size[0]) != 0 ||
    205 	    fdtbus_get_reg(phandle, 1, &addr[1], &size[1]) != 0) {
    206 		aprint_error(": couldn't get registers\n");
    207 		return;
    208 	}
    209 
    210 	sc->sc_dev = self;
    211 	sc->sc_bst = faa->faa_bst;
    212 	if (bus_space_map(sc->sc_bst, addr[0], size[0], 0, &sc->sc_bsh) != 0 ||
    213 	    bus_space_map(sc->sc_bst, addr[1], size[1], 0, &prgeth_bsh) != 0) {
    214 		aprint_error(": couldn't map registers\n");
    215 		return;
    216 	}
    217 	sc->sc_dmat = faa->faa_dmat;
    218 
    219 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
    220 		aprint_error(": failed to decode interrupt\n");
    221 		return;
    222 	}
    223 
    224 	clk_gmac = fdtbus_clock_get(phandle, "stmmaceth");
    225 	clk_in[0] = fdtbus_clock_get(phandle, "clkin0");
    226 	clk_in[1] = fdtbus_clock_get(phandle, "clkin1");
    227 	if (clk_gmac == NULL || clk_in[0] == NULL || clk_in[1] == NULL) {
    228 		aprint_error(": couldn't get clocks\n");
    229 		return;
    230 	}
    231 
    232 	rst_gmac = fdtbus_reset_get(phandle, "stmmaceth");
    233 
    234 	phy_mode = fdtbus_get_string(phandle, "phy-mode");
    235 	if (phy_mode == NULL) {
    236 		aprint_error(": missing 'phy-mode' property\n");
    237 		return;
    238 	}
    239 	phandle_phy = fdtbus_get_phandle(phandle, "phy-handle");
    240 	if (phandle_phy > 0) {
    241 		of_getprop_uint32(phandle_phy, "reg", &phy);
    242 	} else {
    243 		phandle_phy = phandle;
    244 	}
    245 
    246 	if (strncmp(phy_mode, "rgmii", 5) == 0) {
    247 		meson_dwmac_set_mode_rgmii(phandle, sc->sc_bst, prgeth_bsh, clk_in[0]);
    248 	} else if (strcmp(phy_mode, "rmii") == 0) {
    249 		meson_dwmac_set_mode_rmii(phandle, sc->sc_bst, prgeth_bsh);
    250 	} else {
    251 		aprint_error(": unsupported phy-mode '%s'\n", phy_mode);
    252 		return;
    253 	}
    254 
    255 	if (clk_enable(clk_gmac) != 0) {
    256 		aprint_error(": couldn't enable clock\n");
    257 		return;
    258 	}
    259 
    260 	if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) {
    261 		aprint_error(": couldn't de-assert reset\n");
    262 		return;
    263 	}
    264 
    265 	aprint_naive("\n");
    266 	aprint_normal(": Gigabit Ethernet Controller\n");
    267 
    268 	if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET,
    269 	    FDT_INTR_MPSAFE, meson_dwmac_intr, sc,
    270 	    device_xname(sc->sc_dev)) == NULL) {
    271 		aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr);
    272 		return;
    273 	}
    274 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
    275 
    276 	/*
    277 	 * Depending on the DTS, we need to check either the "snps,...",
    278 	 * properties on the ethernet node, or the "reset-..."
    279 	 * properties on the phy node for the MAC reset information.
    280 	 */
    281 
    282 	if (of_hasprop(phandle, "snps,reset-gpio")) {
    283 		if (meson_dwmac_reset_eth(phandle) != 0)
    284 			aprint_error_dev(self, "reset failed\n");
    285 	} else {
    286 		if (meson_dwmac_reset_phy(phandle_phy) != 0)
    287 			aprint_error_dev(self, "PHY reset failed\n");
    288 	}
    289 
    290 	miiclk_rate = clk_get_rate(clk_gmac);
    291 	if (miiclk_rate > 250 * 1000 * 1000)
    292 		miiclk = GMAC_MII_CLK_250_300M_DIV124;
    293 	else if (miiclk_rate > 150 * 1000 * 1000)
    294 		miiclk = GMAC_MII_CLK_150_250M_DIV102;
    295 	else if (miiclk_rate > 100 * 1000 * 1000)
    296 		miiclk = GMAC_MII_CLK_100_150M_DIV62;
    297 	else if (miiclk_rate > 60 * 1000 * 1000)
    298 		miiclk = GMAC_MII_CLK_60_100M_DIV42;
    299 	else if (miiclk_rate > 35 * 1000 * 1000)
    300 		miiclk = GMAC_MII_CLK_35_60M_DIV26;
    301 	else
    302 		miiclk = GMAC_MII_CLK_25_35M_DIV16;
    303 
    304 	dwc_gmac_attach(sc, phy, miiclk);
    305 }
    306 
    307 CFATTACH_DECL_NEW(meson_dwmac, sizeof(struct dwc_gmac_softc),
    308 	meson_dwmac_match, meson_dwmac_attach, NULL, NULL);
    309