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/src/external/gpl3/binutils/dist/opcodes/
ppc-opc.c	3489 #define RSQ RS_EVEN + 1 3490 #define RTQ RSQ 3495 #define RSO RSQ + 1 7533 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, 9671 {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 10102 {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}},
/src/external/gpl3/binutils.old/dist/opcodes/
ppc-opc.c	3489 #define RSQ RS_EVEN + 1 3490 #define RTQ RSQ 3495 #define RSO RSQ + 1 7502 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, 9606 {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 10037 {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}},
/src/external/gpl3/gdb/dist/opcodes/
ppc-opc.c	3411 #define RSQ RS_EVEN + 1 3412 #define RTQ RSQ 3417 #define RSO RSQ + 1 7383 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, 9466 {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 9894 {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}},
/src/external/gpl3/gdb.old/dist/opcodes/
ppc-opc.c	3411 #define RSQ RS_EVEN + 1 3412 #define RTQ RSQ 3417 #define RSO RSQ + 1 7383 {"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, 9455 {"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 9883 {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}},

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Indexes created Wed Mar 04 05:31:52 UTC 2026