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Searched defs:RSRC (Results 1 - 4 of 4) sorted by relevancy

/src/external/gpl3/binutils/dist/opcodes/
d10v-opc.c	101 #define RSRC (UNUSED + 1) 103 #define RSRC_SP (RSRC + 1) 172 { "add", SHORT_2, 1, EITHER, PAR\|WCAR, 0x0200, 0x7e01, { RDST, RSRC } }, 176 { "add3", LONG_L, 1, MU, SEQ\|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 182 { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, 183 { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 201 { "cmp", SHORT_2, 1, EITHER, PAR\|WF0, 0x600, 0x7e01, { RSRC2, RSRC } }, 203 { "cmpeq", SHORT_2, 1, EITHER, PAR\|WF0, 0x400, 0x7e01, { RSRC2, RSRC } }, 211 { "cmpu", SHORT_2, 1, EITHER, PAR\|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } }, 216 { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, [all...]
/src/external/gpl3/binutils.old/dist/opcodes/
d10v-opc.c	101 #define RSRC (UNUSED + 1) 103 #define RSRC_SP (RSRC + 1) 172 { "add", SHORT_2, 1, EITHER, PAR\|WCAR, 0x0200, 0x7e01, { RDST, RSRC } }, 176 { "add3", LONG_L, 1, MU, SEQ\|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 182 { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, 183 { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 201 { "cmp", SHORT_2, 1, EITHER, PAR\|WF0, 0x600, 0x7e01, { RSRC2, RSRC } }, 203 { "cmpeq", SHORT_2, 1, EITHER, PAR\|WF0, 0x400, 0x7e01, { RSRC2, RSRC } }, 211 { "cmpu", SHORT_2, 1, EITHER, PAR\|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } }, 216 { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, [all...]
/src/external/gpl3/gdb.old/dist/opcodes/
d10v-opc.c	101 #define RSRC (UNUSED + 1) 103 #define RSRC_SP (RSRC + 1) 172 { "add", SHORT_2, 1, EITHER, PAR\|WCAR, 0x0200, 0x7e01, { RDST, RSRC } }, 176 { "add3", LONG_L, 1, MU, SEQ\|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 182 { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, 183 { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 201 { "cmp", SHORT_2, 1, EITHER, PAR\|WF0, 0x600, 0x7e01, { RSRC2, RSRC } }, 203 { "cmpeq", SHORT_2, 1, EITHER, PAR\|WF0, 0x400, 0x7e01, { RSRC2, RSRC } }, 211 { "cmpu", SHORT_2, 1, EITHER, PAR\|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } }, 216 { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, [all...]
/src/external/gpl3/gdb/dist/opcodes/
d10v-opc.c	101 #define RSRC (UNUSED + 1) 103 #define RSRC_SP (RSRC + 1) 172 { "add", SHORT_2, 1, EITHER, PAR\|WCAR, 0x0200, 0x7e01, { RDST, RSRC } }, 176 { "add3", LONG_L, 1, MU, SEQ\|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 182 { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, 183 { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, 201 { "cmp", SHORT_2, 1, EITHER, PAR\|WF0, 0x600, 0x7e01, { RSRC2, RSRC } }, 203 { "cmpeq", SHORT_2, 1, EITHER, PAR\|WF0, 0x400, 0x7e01, { RSRC2, RSRC } }, 211 { "cmpu", SHORT_2, 1, EITHER, PAR\|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } }, 216 { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } }, [all...]

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