1 /* $NetBSD: sophgo,sg2042-reset.h,v 1.2 2024/10/31 07:07:45 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 4 /* 5 * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. 6 */ 7 8 #ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ 9 #define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ 10 11 #define RST_MAIN_AP 0 12 #define RST_RISCV_CPU 1 13 #define RST_RISCV_LOW_SPEED_LOGIC 2 14 #define RST_RISCV_CMN 3 15 #define RST_HSDMA 4 16 #define RST_SYSDMA 5 17 #define RST_EFUSE0 6 18 #define RST_EFUSE1 7 19 #define RST_RTC 8 20 #define RST_TIMER 9 21 #define RST_WDT 10 22 #define RST_AHB_ROM0 11 23 #define RST_AHB_ROM1 12 24 #define RST_I2C0 13 25 #define RST_I2C1 14 26 #define RST_I2C2 15 27 #define RST_I2C3 16 28 #define RST_GPIO0 17 29 #define RST_GPIO1 18 30 #define RST_GPIO2 19 31 #define RST_PWM 20 32 #define RST_AXI_SRAM0 21 33 #define RST_AXI_SRAM1 22 34 #define RST_SF0 23 35 #define RST_SF1 24 36 #define RST_LPC 25 37 #define RST_ETH0 26 38 #define RST_EMMC 27 39 #define RST_SD 28 40 #define RST_UART0 29 41 #define RST_UART1 30 42 #define RST_UART2 31 43 #define RST_UART3 32 44 #define RST_SPI0 33 45 #define RST_SPI1 34 46 #define RST_DBG_I2C 35 47 #define RST_PCIE0 36 48 #define RST_PCIE1 37 49 #define RST_DDR0 38 50 #define RST_DDR1 39 51 #define RST_DDR2 40 52 #define RST_DDR3 41 53 #define RST_FAU0 42 54 #define RST_FAU1 43 55 #define RST_FAU2 44 56 #define RST_RXU0 45 57 #define RST_RXU1 46 58 #define RST_RXU2 47 59 #define RST_RXU3 48 60 #define RST_RXU4 49 61 #define RST_RXU5 50 62 #define RST_RXU6 51 63 #define RST_RXU7 52 64 #define RST_RXU8 53 65 #define RST_RXU9 54 66 #define RST_RXU10 55 67 #define RST_RXU11 56 68 #define RST_RXU12 57 69 #define RST_RXU13 58 70 #define RST_RXU14 59 71 #define RST_RXU15 60 72 #define RST_RXU16 61 73 #define RST_RXU17 62 74 #define RST_RXU18 63 75 #define RST_RXU19 64 76 #define RST_RXU20 65 77 #define RST_RXU21 66 78 #define RST_RXU22 67 79 #define RST_RXU23 68 80 #define RST_RXU24 69 81 #define RST_RXU25 70 82 #define RST_RXU26 71 83 #define RST_RXU27 72 84 #define RST_RXU28 73 85 #define RST_RXU29 74 86 #define RST_RXU30 75 87 #define RST_RXU31 76 88 89 #endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */ 90