| /src/usr.bin/uuencode/ |
| uuencode.c | 99 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH)
100 mode = RW & ~umask(RW);
|
| /src/sys/external/bsd/compiler_rt/dist/lib/tsan/tests/rtl/ |
| tsan_test_util.h | 36 RW,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
101 return IsSubLo ? BT::BitMask(0, RW-1)
102 : BT::BitMask(RW, 2*RW-1);
274 // Extract RW low bits of the cell.
275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
277 assert(RW <= RC.width());
278 return eXTR(RC, 0, RW);
280 // Extract RW high bits of the cell.
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
[all...] |
| /src/external/bsd/ntp/dist/include/ |
| ntpd.h | 108 #define RW (CAN_READ|CAN_WRITE)
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| rl78-decode.c | 67 #define RW(x) ((x)+RL78_Reg_AX)
118 #define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
225 int rw AU = (op[0] >> 1) & 0x03;
231 printf (" rw = 0x%x\n", rw);
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
631 int rw AU = (op[0] >> 1) & 0x03;
637 printf (" rw = 0x%x\n", rw);
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| rl78-decode.c | 67 #define RW(x) ((x)+RL78_Reg_AX)
118 #define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
225 int rw AU = (op[0] >> 1) & 0x03;
231 printf (" rw = 0x%x\n", rw);
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
631 int rw AU = (op[0] >> 1) & 0x03;
637 printf (" rw = 0x%x\n", rw);
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| rl78-decode.c | 67 #define RW(x) ((x)+RL78_Reg_AX)
118 #define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
225 int rw AU = (op[0] >> 1) & 0x03;
231 printf (" rw = 0x%x\n", rw);
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
631 int rw AU = (op[0] >> 1) & 0x03;
637 printf (" rw = 0x%x\n", rw);
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| rl78-decode.c | 67 #define RW(x) ((x)+RL78_Reg_AX)
118 #define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
129 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
225 int rw AU = (op[0] >> 1) & 0x03;
231 printf (" rw = 0x%x\n", rw);
235 ID(add); W(); DR(AX); SRW(rw); Fzac;
631 int rw AU = (op[0] >> 1) & 0x03;
637 printf (" rw = 0x%x\n", rw);
[all...] |
| /src/libexec/getty/ |
| gettytab.h | 156 #define RW gettyflags[11].value
|
| /src/sys/dev/microcode/aic7xxx/ |
| aicasm_symbol.h | 71 RW = 0x03
|
| /src/usr.sbin/lpr/common_source/ |
| common.c | 99 long RW; /* open LP for reading and writing */
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenSchedule.cpp | 577 // Visit each RW in the sequence selected by the current variant.
601 for (Record *RW : RWs) {
602 if (RW->isSubClassOf("SchedWrite"))
603 scanSchedRW(RW, SWDefs, RWSet);
605 assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
606 scanSchedRW(RW, SRDefs, RWSet);
681 CodeGenSchedRW &RW = getSchedRW(MatchDef);
682 if (RW.IsAlias)
684 RW.Aliases.push_back(ADef);
724 RWVec, [Def](const CodeGenSchedRW &RW) { return RW.TheDef == Def; })
[all...] |
| /src/external/gpl3/gdb/dist/sim/d10v/ |
| d10v-sim.h | 460 #define RW(x) get_word (dmem_addr (sd, cpu, x))
|
| /src/external/gpl3/gdb.old/dist/sim/cr16/ |
| cr16-sim.h | 384 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
391 return (RW (addr) << 16) | RW (addr + 2);
|
| /src/external/gpl3/gdb.old/dist/sim/d10v/ |
| d10v-sim.h | 460 #define RW(x) get_word (dmem_addr (sd, cpu, x))
|
| /src/external/gpl3/gdb/dist/sim/cr16/ |
| cr16-sim.h | 384 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
391 return (RW (addr) << 16) | RW (addr + 2);
|
| /src/sys/dev/pci/ |
| pci_subr.c | 4497 #undef RW
|
| /src/sys/dev/ic/ |
| athnreg.h | 1486 #define RW(var, field, val) \
|
| rtwnreg.h | 1049 #define RW(var, field, val) \
|
