| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 41 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
3507 /* The RY field of the SE_RR form instruction. */
3508 #define RY ARX + 1
3509 #define RZ RY
3513 #define ARY RY + 1
10141 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
10142 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
10144 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
10145 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
10146 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 41 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
3507 /* The RY field of the SE_RR form instruction. */
3508 #define RY ARX + 1
3509 #define RZ RY
3513 #define ARY RY + 1
10076 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
10077 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
10079 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
10080 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
10081 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 41 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
3429 /* The RY field of the SE_RR form instruction. */
3430 #define RY ARX + 1
3431 #define RZ RY
3435 #define ARY RY + 1
9933 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9934 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
9936 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9937 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9938 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 41 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
3429 /* The RY field of the SE_RR form instruction. */
3430 #define RY ARX + 1
3431 #define RZ RY
3435 #define ARY RY + 1
9922 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9923 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
9925 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9926 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
9927 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
[all...] |
