| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 159 unsigned Ra) {
160 if (Rd == Ra)
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
168 LLVM_DEBUG(dbgs() << "Ra is a physical reg:"
169 << Register::isPhysicalRegister(Ra) << '\n');
174 PBQPRAGraph::NodeId node2 = G.getMetadata().getNodeIdForVReg(Ra);
187 const LiveInterval &la = LIs.getInterval(Ra);
243 unsigned Ra) {
247 if (Chains.count(Ra)) {
248 if (Rd != Ra) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMCCodeEmitter.cpp | 114 MCRegister Ra;
117 Ra = RISCV::X6;
120 Ra = MI.getOperand(0).getReg();
123 Ra = RISCV::X1;
126 Ra = MI.getOperand(0).getReg();
134 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
136 .addReg(Ra)
143 // Emit JALR X0, Ra, 0
144 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
146 // Emit JALR Ra, Ra,
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| d30v-opc.c | 348 #define Ra (UNUSED + 1)
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) *
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| d30v-opc.c | 348 #define Ra (UNUSED + 1)
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) *
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| d30v-opc.c | 348 #define Ra (UNUSED + 1)
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) *
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| d30v-opc.c | 348 #define Ra (UNUSED + 1)
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) *
[all...] |
| /src/external/gpl3/gdb/dist/sim/arm/ |
| thumbemu.c | 1715 ARMword Ra = ntBITS (12, 15);
1719 // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
1725 tASSERT (Ra != 15);
1738 res += state->Reg[Ra];
1746 // MLS<c> <Rd>,<Rn>,<Rm>,<Ra>
1747 state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]);
1753 if (Ra == 15)
1757 // MLA<c> <Rd>,<Rn>,<Rm>,<Ra>
1758 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra];
|
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| thumbemu.c | 1715 ARMword Ra = ntBITS (12, 15);
1719 // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
1725 tASSERT (Ra != 15);
1738 res += state->Reg[Ra];
1746 // MLS<c> <Rd>,<Rn>,<Rm>,<Ra>
1747 state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]);
1753 if (Ra == 15)
1757 // MLA<c> <Rd>,<Rn>,<Rm>,<Ra>
1758 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra];
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 2497 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 12742 unsigned Rd, Rn, Rm, Ra;
12747 Ra = inst.operands[3].reg;
12752 reject_bad_reg (Ra);
12757 inst.instruction |= Ra << 12;
|
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 12745 unsigned Rd, Rn, Rm, Ra;
12750 Ra = inst.operands[3].reg;
12755 reject_bad_reg (Ra);
12760 inst.instruction |= Ra << 12;
|
