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Searched
defs:RdLo
(Results
1 - 7
of
7
) sorted by relevancy
/src/external/gpl3/gdb.old/dist/sim/arm/
armemu.c
5964
/* If (result ==
RdLo
) and (state->Reg[nRdLo] == 0),
5965
or (result >
RdLo
) then we have no carry. */
5982
ARMword RdHi = 0,
RdLo
= 0, Rm;
6037
RdLo
= Add32 (lo, (mid1 << 16), &carry);
6039
RdLo
= Add32 (
RdLo
, (mid2 << 16), &carry);
6046
RdLo
= ~
RdLo
;
6048
if (
RdLo
== 0xFFFFFFFF)
6050
RdLo
= 0
[
all
...]
iwmmxt.c
929
ARMword
RdLo
= state->Reg [BITS (12, 15)];
941
wR [BITS (0, 3)] = (RdHi << 32) |
RdLo
;
/src/external/gpl3/gdb/dist/sim/v850/
simops.c
332
unsigned long
RdLo
;
360
RdLo
= Add32 (lo, (mid1 << 16), & carry);
362
RdLo
= Add32 (
RdLo
, (mid2 << 16), & carry);
369
RdLo
= ~
RdLo
;
371
if (
RdLo
== 0xFFFFFFFF)
373
RdLo
= 0;
377
RdLo
+= 1;
382
State.regs[ OP[1] ] =
RdLo
;
[
all
...]
/src/external/gpl3/gdb.old/dist/sim/v850/
simops.c
332
unsigned long
RdLo
;
360
RdLo
= Add32 (lo, (mid1 << 16), & carry);
362
RdLo
= Add32 (
RdLo
, (mid2 << 16), & carry);
369
RdLo
= ~
RdLo
;
371
if (
RdLo
== 0xFFFFFFFF)
373
RdLo
= 0;
377
RdLo
+= 1;
382
State.regs[ OP[1] ] =
RdLo
;
[
all
...]
/src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp
8288
unsigned
RdLo
= Inst.getOperand(1).getReg();
8289
if(RdHi ==
RdLo
) {
8291
"unpredictable instruction, RdHi and
RdLo
must be different");
/src/external/gpl3/binutils/dist/gas/config/
tc-arm.c
9539
MAR{cond} acc0, <
RdLo
>, <RdHi> == MCRR{cond} p0, #0, <
RdLo
>, <RdHi>, c0
9540
MRA{cond} acc0, <
RdLo
>, <RdHi> == MRRC{cond} p0, #0, <
RdLo
>, <RdHi>, c0
10137
UMULL
RdLo
, RdHi, Rm, Rs
10138
SMULL
RdLo
, RdHi, Rm, Rs
10139
UMLAL
RdLo
, RdHi, Rm, Rs
10140
SMLAL
RdLo
, RdHi, Rm, Rs. */
10150
/* rdhi and
rdlo
must be different. */
10152
as_tsktsk (_("rdhi and
rdlo
must be different"))
[
all
...]
/src/external/gpl3/binutils.old/dist/gas/config/
tc-arm.c
9542
MAR{cond} acc0, <
RdLo
>, <RdHi> == MCRR{cond} p0, #0, <
RdLo
>, <RdHi>, c0
9543
MRA{cond} acc0, <
RdLo
>, <RdHi> == MRRC{cond} p0, #0, <
RdLo
>, <RdHi>, c0
10140
UMULL
RdLo
, RdHi, Rm, Rs
10141
SMULL
RdLo
, RdHi, Rm, Rs
10142
UMLAL
RdLo
, RdHi, Rm, Rs
10143
SMLAL
RdLo
, RdHi, Rm, Rs. */
10153
/* rdhi and
rdlo
must be different. */
10155
as_tsktsk (_("rdhi and
rdlo
must be different"))
[
all
...]
Completed in 47 milliseconds
Indexes created Sun May 03 00:22:47 UTC 2026