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  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Checkers/
Taint.cpp 136 TaintedSubRegions Regs = SavedRegs ? *SavedRegs : F.getEmptyMap();
138 Regs = F.add(Regs, SubRegion, Kind);
139 ProgramStateRef NewState = State->set<DerivedSymTaint>(ParentSym, Regs);
202 if (const TaintedSubRegions *Regs =
205 for (auto I : *Regs) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRegisterInfo.cpp 144 static const unsigned Regs[2][2] = {
149 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
CallLowering.h 62 SmallVector<Register, 4> Regs;
74 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
77 : BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()),
79 if (!Regs.empty() && Flags.empty())
83 (Regs.empty() || Regs[0] == 0)) &&
87 ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue,
90 : ArgInfo(Regs, OrigValue.getType(), Flags, IsFixed, &OrigValue) {
    [all...]
IRTranslator.h 627 auto Regs = getOrCreateVRegs(Val);
628 if (Regs.empty())
630 assert(Regs.size() == 1 &&
632 return Regs[0];
LegalizationArtifactCombiner.h 683 SmallVector<Register, 8> Regs;
686 Regs.push_back(MergeI->getOperand(Idx).getReg());
689 Builder.buildMerge(DefReg, Regs);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
RDFRegisters.h 135 return AliasInfos[U].Regs;
153 BitVector Regs;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64LowerHomogeneousPrologEpilog.cpp 129 static std::string getFrameHelperName(SmallVectorImpl<unsigned> &Regs,
147 for (auto Reg : Regs)
241 /// Return a unique function if a helper can be formed with the given Regs
268 /// @param Regs callee save regs that the helper will handle
272 SmallVectorImpl<unsigned> &Regs,
275 assert(Regs.size() >= 2);
276 auto Name = getFrameHelperName(Regs, Type, FpOffset);
286 int Size = (int)Regs.size();
292 Regs.begin(), std::find(Regs.begin(), Regs.end(), AArch64::LR))
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.cpp 383 auto Regs = RC.getRegisters();
406 SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
409 NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
414 if (NextSpillReg == Regs.end()) { // Registers exhausted
SILoadStoreOptimizer.cpp 536 AddressRegs Regs = getRegs(Opc, TII);
539 for (unsigned J = 0; J < Regs.NumVAddrs; J++)
542 if (Regs.Addr)
545 if (Regs.SBase)
548 if (Regs.SRsrc)
551 if (Regs.SOffset)
554 if (Regs.VAddr)
557 if (Regs.SSamp)
1334 AddressRegs Regs = getRegs(Opcode, *TII);
1336 if (Regs.VAddr
    [all...]
SIInstrInfo.cpp 2613 SmallVector<Register, 8> Regs;
2616 Regs.push_back(DstElt);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUPALMetadata.cpp 162 auto Regs = getRegisters();
163 auto It = Regs.find(MsgPackDoc.getNode(Reg));
164 if (It == Regs.end())
648 auto Regs = getRegisters();
649 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I) {
650 if (I != Regs.begin())
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 158 // Return true to make these hints the only regs available to
240 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
242 return Regs->getCalleeSavedRegs(MF);
250 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
251 return Regs->getCallPreservedMask(MF, CC);
259 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
262 for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true);
267 for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true);
439 // Demand an arbitrary margin of free regs.
451 SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters()
    [all...]
SystemZISelDAGToDAG.cpp 705 SDValue Regs[2];
706 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) &&
707 Regs[0].getNode() && Regs[1].getNode()) {
709 Base = Regs[I];
710 Index = Regs[1 - I];
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InlineAsmLowering.cpp 38 /// Regs - If this is a register or register class operand, this
40 SmallVector<Register, 1> Regs;
137 OpInfo.Regs.push_back(R);
399 if (OpInfo.Regs.empty()) {
410 OpInfo.Regs.size());
411 if (OpInfo.Regs.front().isVirtual()) {
416 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
422 for (Register Reg : OpInfo.Regs) {
545 if (OpInfo.Regs.empty()) {
552 unsigned NumRegs = OpInfo.Regs.size()
    [all...]
IRTranslator.cpp 176 auto *Regs = VMap.getVRegs(Val);
182 Regs->push_back(0);
183 return *Regs;
1270 ArrayRef<Register> Regs = getOrCreateVRegs(LI);
1278 assert(Regs.size() == 1 && "swifterror should be single pointer");
1281 MIRBuilder.buildCopy(Regs[0], VReg);
1289 Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr;
1290 for (unsigned i = 0; i < Regs.size(); ++i) {
1299 Ptr, Flags, MRI->getType(Regs[i]).getSizeInBytes(),
1302 MIRBuilder.buildLoad(Regs[i], Addr, *MMO)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.h 854 SmallVector<unsigned, 4> Regs;
864 RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt, EVT valuevt,
878 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
879 RegCount.push_back(RHS.Regs.size());
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVFrameLowering.cpp 804 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
806 for (unsigned i = 0; Regs[i]; ++i)
807 if (RISCV::FPR16RegClass.contains(Regs[i]) ||
808 RISCV::FPR32RegClass.contains(Regs[i]) ||
809 RISCV::FPR64RegClass.contains(Regs[i]))
810 SavedRegs.set(Regs[i]);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 178 ArrayRef<std::pair<unsigned, bool>> Regs,
184 ArrayRef<std::pair<unsigned, bool>> Regs,
582 /// Return the first register of class \p RegClass that is not in \p Regs.
614 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
616 for (const std::pair<unsigned, bool> &R : Regs)
623 /// Regs as the register operands that would be loaded / stored. It returns
629 ArrayRef<std::pair<unsigned, bool>> Regs,
631 unsigned NumRegs = Regs.size();
645 if (isThumb1 && ContainsReg(Regs, Base)) {
685 NewBase = Regs[NumRegs-1].first
    [all...]
ARMFrameLowering.cpp 59 // | callee-saved fp/simd regs |
1084 SmallVector<RegAndKill, 4> Regs;
1111 Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
1114 if (Regs.empty())
1117 llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) {
1121 if (Regs.size() > 1 || StrOpc== 0) {
1126 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1127 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1128 } else if (Regs.size() == 1)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
MipsDisassembler.cpp 2426 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2443 Inst.addOperand(MCOperand::createReg(Regs[i]));
2454 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2468 Inst.addOperand(MCOperand::createReg(Regs[i]));
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
89 const std::deque<CodeGenRegister> &Regs,
107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
218 const CodeGenRegister::Vec &Regs = RC.getMembers();
220 if (Regs.empty() || RC.Artificial)
383 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
389 for (auto &RE : Regs) {
405 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");
450 for (auto &RE : Regs) {
510 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor)
    [all...]
CodeGenRegisters.cpp 209 RegUnitIterator(const CodeGenRegister::Vec &Regs):
210 RegI(Regs.begin()), RegE(Regs.end()) {
391 // SR is composed of multiple sub-regs. Find their names in this register.
1121 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
1122 llvm::sort(Regs, LessRecordRegister());
1124 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1125 getReg(Regs[i]);
1580 CodeGenRegister::Vec Regs;
1609 const CodeGenRegister::Vec &Regs = RegClass.getMembers()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveDebugVariables.cpp 1534 SmallVector<Register, 4> Regs;
1537 Regs.push_back(LocMO.getReg());
1538 if (Regs.empty())
1546 if (any_of(Regs, [&I, &TRI](Register &Reg) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/
SystemZAsmParser.cpp 865 const unsigned *Regs;
867 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
868 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
869 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
870 case GR128Reg: Regs = SystemZMC::GR128Regs; break;
871 case FP32Reg: Regs = SystemZMC::FP32Regs; break;
872 case FP64Reg: Regs = SystemZMC::FP64Regs; break;
873 case FP128Reg: Regs = SystemZMC::FP128Regs; break;
874 case VR32Reg: Regs = SystemZMC::VR32Regs; break;
875 case VR64Reg: Regs = SystemZMC::VR64Regs; break
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 361 /// #3 ensures invariant regs with respect to current loop can be combined
1061 SmallPtrSetImpl<const SCEV *> &Regs,
1071 SmallPtrSetImpl<const SCEV *> &Regs);
1073 SmallPtrSetImpl<const SCEV *> &Regs,
1184 SmallPtrSet<const SCEV *, 4> Regs;
1241 SmallPtrSetImpl<const SCEV *> &Regs) {
1288 if (!Regs.count(AR->getOperand(1))) {
1289 RateRegister(F, AR->getOperand(1), Regs);
1309 /// one of those regs an instant loser.
1311 SmallPtrSetImpl<const SCEV *> &Regs,
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