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    Searched defs:Rs (Results 1 - 25 of 26) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVMergeBaseOffset.cpp 138 Register Rs = TailAdd.getOperand(1).getReg();
140 Register Reg = Rs == GAReg ? Rt : Rs;
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ScalarEvolutionDivision.cpp 149 SmallVector<const SCEV *, 2> Qs, Rs;
161 Rs.push_back(R);
166 Remainder = Rs[0];
171 Remainder = SE.getAddExpr(Rs);
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/Disassembler/
MSP430Disassembler.cpp 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) {
155 switch (Rs) {
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4);
184 return DecodeSrcAddrMode(Rs, As);
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4);
190 return DecodeSrcAddrMode(Rs, As);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCompound.cpp 110 // P0 = cmp.eq(Rs,#u2)
122 // Rd = Rs
163 // Rd=Rs ; jump #r9:2
201 MCOperand Rs, Rt;
223 Rs = L.getOperand(1);
229 CompoundInsn->addOperand(Rs);
236 Rs = L.getOperand(1);
242 CompoundInsn->addOperand(Rs);
249 Rs = L.getOperand(1);
255 CompoundInsn->addOperand(Rs);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.cpp 409 MCOperand &Rs = Inst.getOperand(1);
410 assert(Rs.isReg() && "Expected register and none was found");
411 unsigned Reg = RI->getEncodingValue(Rs.getReg());
416 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
486 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
537 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
HexagonSplitDouble.cpp 103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
147 const USet &Rs = I.second;
148 if (Rs.find(Reg) != Rs.end())
374 Register Rs = MI->getOperand(1).getReg();
376 return profit(Rs) + profit(Rt);
476 USet &Rs) {
560 Rs.insert(DP.begin(), End);
561 Rs.insert(CmpR1);
562 Rs.insert(CmpR2)
    [all...]
HexagonConstExtenders.cpp 277 // In memw(Rs+##V), the ##V could be replaced by a register Rt to
278 // form the rr mode: memw(Rt+Rs<<0). In such case, however, the
280 // another instruction memw(Rs+##V+4), it would need a different Rt.
281 // Now, if Rt was initialized as "##V+Rs<<0", both of these
288 // Include shifting the Rs to account for the ur addressing mode:
289 // ##Val + Rs << S
290 // ##Val - Rs
291 Register Rs;
296 ExtExpr(Register RS, bool NG, unsigned SH) : Rs(RS), S(SH), Neg(NG) {
    [all...]
HexagonFrameLowering.cpp 143 // Rd = PS_alloca Rs, A
146 // Rs - minimum size (the actual allocated can be larger to accommodate
1505 MachineFunction &MF, RegScavenger *RS) const {
2126 RegScavenger *RS) const {
2172 RS->addScavengingFrameIndex(NewFI);
2177 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2541 // Rd = alloca Rs, #A
2543 // If Rs and Rd are different registers, use this sequence:
2544 // Rd = sub(r29, Rs)
2545 // r29 = sub(r29, Rs)
    [all...]
HexagonInstrInfo.cpp 1260 Register Rs = Op2.getReg();
1266 if (Rd != Rs)
1269 .addReg(Rs, K2);
3353 // P0 = cmp.eq(Rs,#u2)
3364 // Rd = Rs
3402 // Rd=Rs ; jump #r9:2
3827 // Rd = memw(Rs+#u4:2)
3828 // Rd = memub(Rs+#u4:0)
3841 // Rd = memw(Rs+#u4:2)
3850 // Rd = memub(Rs+#u4:0
    [all...]
  /src/external/gpl3/gdb/dist/sim/arm/
thumbemu.c 2076 | ((tinstr & 0x0038) >> 3) /* Rs */
2084 0xE0900000, /* ADDS Rd,Rs,Rn */
2085 0xE0500000, /* SUBS Rd,Rs,Rn */
2086 0xE2900000, /* ADDS Rd,Rs,#imm3 */
2087 0xE2500000 /* SUBS Rd,Rs,#imm3 */
2093 | ((tinstr & 0x0038) << (16 - 3)) /* Rs */
2140 { 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
2141 { 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
2142 { 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
2143 { 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
    [all...]
armemu.c 4544 ARMsdword Rs = state->Reg[MULACCReg];
4548 if (Rs & (1 << 31))
4549 Rs -= 1ULL << 32;
4550 state->Accumulator += Rm * Rs;
6004 ARMword Rs = state->Reg[nRs];
6019 sign = (Rm ^ Rs) & 0x80000000;
6024 if (((ARMsword) Rs) < 0)
6025 Rs = -Rs;
6030 lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF))
    [all...]
iwmmxt.c 984 ARMword Rs = state->Reg [BITS (12, 15)];
999 a = SUBSTR (Rs, ARMword, 16, 31);
1012 a = SUBSTR (Rs, ARMword, 0, 15);
1033 ARMword Rs;
1055 Rs = state->Reg [BITS (12, 15)];
1057 Rs >>= 16;
1059 Rs &= 0xffff;
1064 if (Rs & (1 << 15))
1065 Rs -= 1 << 16;
1067 Rm *= Rs;
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/arm/
thumbemu.c 2076 | ((tinstr & 0x0038) >> 3) /* Rs */
2084 0xE0900000, /* ADDS Rd,Rs,Rn */
2085 0xE0500000, /* SUBS Rd,Rs,Rn */
2086 0xE2900000, /* ADDS Rd,Rs,#imm3 */
2087 0xE2500000 /* SUBS Rd,Rs,#imm3 */
2093 | ((tinstr & 0x0038) << (16 - 3)) /* Rs */
2140 { 0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
2141 { 0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
2142 { 0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
2143 { 0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
    [all...]
armemu.c 4544 ARMsdword Rs = state->Reg[MULACCReg];
4548 if (Rs & (1 << 31))
4549 Rs -= 1ULL << 32;
4550 state->Accumulator += Rm * Rs;
6004 ARMword Rs = state->Reg[nRs];
6019 sign = (Rm ^ Rs) & 0x80000000;
6024 if (((ARMsword) Rs) < 0)
6025 Rs = -Rs;
6030 lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF))
    [all...]
iwmmxt.c 984 ARMword Rs = state->Reg [BITS (12, 15)];
999 a = SUBSTR (Rs, ARMword, 16, 31);
1012 a = SUBSTR (Rs, ARMword, 0, 15);
1033 ARMword Rs;
1055 Rs = state->Reg [BITS (12, 15)];
1057 Rs >>= 16;
1059 Rs &= 0xffff;
1064 if (Rs & (1 << 15))
1065 Rs -= 1 << 16;
1067 Rm *= Rs;
    [all...]
  /src/external/bsd/mdocml/dist/
mdoc.h 152 struct mdoc_rs Rs;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 1337 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1349 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1373 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1385 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1394 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
MipsDisassembler.cpp 636 InsnType Rs = fieldFromInstruction(insn, 16, 5);
639 Rs)));
641 Rs)));
650 InsnType Rs = fieldFromInstruction(insn, 21, 5);
653 Rs)));
655 Rs)));
671 // BOVC if rs >= rt
672 // BEQZALC if rs == 0 && rt != 0
673 // BEQC if rs < rt && rs !=
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp 1407 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1630 MCOperand &Rs = Inst.getOperand(2);
1640 TmpInst.addOperand(Rs);
1650 MCOperand &Rs = Inst.getOperand(2);
1660 TmpInst.addOperand(Rs);
1670 MCOperand &Rs = Inst.getOperand(2);
1680 TmpInst.addOperand(Rs);
1693 MCOperand &Rs = Inst.getOperand(1);
1710 TmpInst.addOperand(Rs);
1723 if (Value == 0) { // convert to $Rd = $Rs
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 3308 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3312 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3527 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3529 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3534 .addReg(Rs)
3536 Rs = Tmp;
3539 .addReg(Rs)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp 1513 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1518 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 4320 unsigned Rs = Inst.getOperand(0).getReg();
4323 if (RI->isSubRegisterEq(Rt, Rs) ||
4324 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
4333 unsigned Rs = Inst.getOperand(0).getReg();
4337 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
4338 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
  /src/external/gpl3/gdb/dist/sim/aarch64/
simulator.c 1547 unsigned rs = INSTR (20, 16); local
1561 aarch64_set_reg_u64 (cpu, rs, NO_SP, 0); /* Always exclusive... */
2768 unsigned rs = INSTR (9, 5); local
2779 aarch64_get_reg_u8 (cpu, rs, NO_SP));
2785 aarch64_get_reg_u16 (cpu, rs, NO_SP));
2791 aarch64_get_reg_u32 (cpu, rs, NO_SP));
2797 aarch64_get_reg_u64 (cpu, rs, NO_SP));
2993 unsigned Rs = INSTR (9, 5);
3004 aarch64_set_vec_u8 (cpu, Vd, i, aarch64_get_reg_u8 (cpu, Rs, NO_SP));
3009 aarch64_set_vec_u16 (cpu, Vd, i, aarch64_get_reg_u16 (cpu, Rs, NO_SP))
7930 unsigned rs = INSTR (9, 5); local
8402 unsigned rs = INSTR (9, 5); local
8479 unsigned rs = INSTR (9, 5); local
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/aarch64/
simulator.c 1547 unsigned rs = INSTR (20, 16); local
1561 aarch64_set_reg_u64 (cpu, rs, NO_SP, 0); /* Always exclusive... */
2768 unsigned rs = INSTR (9, 5); local
2779 aarch64_get_reg_u8 (cpu, rs, NO_SP));
2785 aarch64_get_reg_u16 (cpu, rs, NO_SP));
2791 aarch64_get_reg_u32 (cpu, rs, NO_SP));
2797 aarch64_get_reg_u64 (cpu, rs, NO_SP));
2993 unsigned Rs = INSTR (9, 5);
3004 aarch64_set_vec_u8 (cpu, Vd, i, aarch64_get_reg_u8 (cpu, Rs, NO_SP));
3009 aarch64_set_vec_u16 (cpu, Vd, i, aarch64_get_reg_u16 (cpu, Rs, NO_SP))
7930 unsigned rs = INSTR (9, 5); local
8402 unsigned rs = INSTR (9, 5); local
8479 unsigned rs = INSTR (9, 5); local
    [all...]
  /src/external/gpl3/binutils/dist/gas/config/
tc-arm.c 5426 (LSL|LSR|ASL|ASR|ROR) Rs
10137 UMULL RdLo, RdHi, Rm, Rs
10138 SMULL RdLo, RdHi, Rm, Rs
10139 UMLAL RdLo, RdHi, Rm, Rs
10140 SMLAL RdLo, RdHi, Rm, Rs. */
10347 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
10402 SMLAxy{cond} Rd,Rm,Rs,Rn
10403 SMLAWy{cond} Rd,Rm,Rs,Rn
10416 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10433 SMULxy{cond} Rd,Rm,Rs
15477 enum neon_shape rs; local
15624 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL); local
15642 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); local
15661 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL); local
15817 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); local
15896 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL); local
15949 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); local
15964 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); local
15999 enum neon_shape rs; local
16033 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); local
16222 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL); local
16242 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); local
16334 enum neon_shape rs; local
16715 enum neon_shape rs; local
16736 enum neon_shape rs; local
16781 enum neon_shape rs; local
16802 enum neon_shape rs; local
16861 enum neon_shape rs; local
16882 enum neon_shape rs; local
16933 enum neon_shape rs; local
17042 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); local
17061 enum neon_shape rs = (three_ops_form local
17149 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); local
17158 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); local
17478 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL); local
17502 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); local
17525 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL); local
17593 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL); local
17704 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); local
17714 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); local
17733 enum neon_shape rs; local
17778 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); local
17830 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); local
17858 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL); local
17885 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); local
17893 enum neon_shape rs; local
17920 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); local
17940 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL); local
17964 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL); local
17993 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); local
18011 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); local
18039 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); local
18054 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); local
18069 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); local
18086 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS, local
18134 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); local
18157 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); local
18193 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL); local
18260 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); local
18280 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL); local
18320 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL); local
18328 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); local
18338 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); local
18350 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); local
18367 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL); local
18376 enum neon_shape rs; local
18406 enum neon_shape rs; local
18432 enum neon_shape rs; local
18457 enum neon_shape rs; local
18775 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL); local
18868 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, local
19198 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD, local
19311 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL); local
19368 enum neon_shape rs; local
19421 enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL); local
19535 enum neon_shape rs; local
19683 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL); local
19708 enum neon_shape rs; local
19741 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL); local
19765 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL); local
19913 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR, local
20282 enum neon_shape rs; local
20314 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL); local
20350 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); local
20360 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); local
20379 enum neon_shape rs; local
20392 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); local
20402 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); local
20415 enum neon_shape rs; local
20432 enum neon_shape rs; local
20446 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); local
20455 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL); local
21046 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL); local
21213 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL); local
21231 enum neon_shape rs; local
21263 enum neon_shape rs; local
21316 enum neon_shape rs; local
21387 enum neon_shape rs; local
21415 enum neon_shape rs; local
21436 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); local
21448 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); local
21860 enum neon_shape rs = neon_select_shape (NS_PQI, NS_PDI, NS_PFI, NS_NULL); local
21876 enum neon_shape rs = neon_select_shape (NS_PQQI, NS_PDDI, NS_PFFI, NS_NULL); local
21892 enum neon_shape rs = neon_select_shape (NS_PQQQI, NS_PDDDI, NS_PFFFI, NS_NULL); local
22096 enum neon_shape rs; local
22124 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); local
28695 int rs = newval & 0xf; local
28893 int rd, rs; local
    [all...]

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