| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVMergeBaseOffset.cpp | 139 Register Rt = TailAdd.getOperand(2).getReg();
140 Register Reg = Rs == GAReg ? Rt : Rs;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 201 MCOperand Rs, Rt;
211 Rt = L.getOperand(0);
216 CompoundInsn->addOperand(Rt);
222 Rt = L.getOperand(0);
228 CompoundInsn->addOperand(Rt);
237 Rt = L.getOperand(2);
243 CompoundInsn->addOperand(Rt);
250 Rt = L.getOperand(2);
256 CompoundInsn->addOperand(Rt);
263 Rt = L.getOperand(2)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 370 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
374 MCOperand &Rt = Inst.getOperand(3);
375 assert(Rt.isReg() && "Expected register and none was found");
376 unsigned Reg = RI->getEncodingValue(Rt.getReg());
381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
385 MCOperand &Rt = Inst.getOperand(2);
386 assert(Rt.isReg() && "Expected register and none was found");
387 unsigned Reg = RI->getEncodingValue(Rt.getReg());
392 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI))
[all...] |
| HexagonSplitDouble.cpp | 375 Register Rt = MI->getOperand(2).getReg();
376 return profit(Rs) + profit(Rt);
|
| HexagonInstrInfo.cpp | 1261 Register Rt = Op3.getReg();
1268 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1270 if (Rd != Rt)
1273 .addReg(Rt, K3);
3950 // memw(Rs+#u4:2) = Rt
3951 // memb(Rs+#u4:0) = Rt
3955 // memw(r29+#u5:2) = Rt
3963 // memw(Rs+#u4:2) = Rt
3971 // memb(Rs+#u4:0) = Rt
3981 // memh(Rs+#u3:1) = Rt
[all...] |
| /src/external/gpl3/gdb/dist/sim/arm/ |
| thumbemu.c | 321 ARMword Rt = ntBITS (12, 15);
328 tASSERT (Rt2 == Rt + 1);
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
350 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
359 * ainstr |= (Rt << 12);
1129 ARMword Rt = ntBITS (12, 15);
1135 tASSERT (Rt != 15);
1137 /* LDRB<c> <Rt>,<label> => 1111 1000 U001 1111 */
1144 /* LDRB<c>.W <Rt>,[<Rn>{,#<imm12>}] => 1111 1000 1001 rrrr *
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| thumbemu.c | 321 ARMword Rt = ntBITS (12, 15);
328 tASSERT (Rt2 == Rt + 1);
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
350 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
359 * ainstr |= (Rt << 12);
1129 ARMword Rt = ntBITS (12, 15);
1135 tASSERT (Rt != 15);
1137 /* LDRB<c> <Rt>,<label> => 1111 1000 U001 1111 */
1144 /* LDRB<c>.W <Rt>,[<Rn>{,#<imm12>}] => 1111 1000 1001 rrrr *
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
472 assert(isARMLowRegister(Rt));
485 .addReg(Rt, IsStore ? 0 : RegState::Define);
|
| ARMBaseInstrInfo.cpp | 3472 Register Rt = MI.getOperand(0).getReg();
3474 return (Rt == Rm) ? 4 : 3;
3479 Register Rt = MI.getOperand(0).getReg();
3481 if (Rt == Rm)
3509 Register Rt = MI.getOperand(0).getReg();
3513 if (Rt == Rm)
3521 Register Rt = MI.getOperand(0).getReg();
3523 return (Rt == Rm) ? 3 : 2;
3544 Register Rt = MI.getOperand(0).getReg();
3545 if (Rt == Rm
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 1075 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1085 // Rt is an immediate in prefetch.
1086 Inst.addOperand(MCOperand::createImm(Rt));
1096 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1103 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1107 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1111 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1115 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1119 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1123 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 671 // BOVC if rs >= rt
672 // BEQZALC if rs == 0 && rt != 0
673 // BEQC if rs < rt && rs != 0
676 InsnType Rt = fieldFromInstruction(insn, 16, 5);
680 if (Rs >= Rt) {
683 } else if (Rs != 0 && Rs < Rt) {
694 Rt)));
704 InsnType Rt = fieldFromInstruction(insn, 21, 5);
708 if (Rs >= Rt) {
711 Rt)));
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 1391 MCOperand &Rt = Inst.getOperand(1);
1394 TmpInst.addOperand(Rt);
1395 TmpInst.addOperand(Rt);
1407 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1812 MCOperand &Rt = Inst.getOperand(2);
1813 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1818 Rt.setReg(matchRegister(RegPair));
1823 Rt.setReg(matchRegister(RegPair));
1832 MCOperand &Rt = Inst.getOperand(3);
1833 unsigned int RegNum = RI->getEncodingValue(Rt.getReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 3162 // copy_u_w $rt, $ws, $n
3163 // mtc1 $rt, $fd
3416 // sld.df inteprets $rt modulo the number of columns so we only need to negate
3515 Register Rt = MI.getOperand(1).getReg();
3540 .addReg(Rt)
3580 Register Rt = RegInfo.createVirtualRegister(RC);
3583 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3589 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3590 Rt = Tmp;
3593 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1857 // On stores, the writeback operand precedes Rt.
1874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1877 // On loads, the writeback operand comes after Rt.
1908 if (writeback && (Rn == 15 || Rn == Rt))
1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2006 unsigned Rt2 = Rt + 1;
2010 // For {LD,ST}RD, Rt must be even, else undefined.
2018 if (Rt & 0x1) S = MCDisassembler::SoftFail;
2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 4200 // the Rt == Rt2. All of those are undefined behaviour.
4207 unsigned Rt = Inst.getOperand(1).getReg();
4210 if (RI->isSubRegisterEq(Rn, Rt))
4224 unsigned Rt = Inst.getOperand(0).getReg();
4226 if (Rt == Rt2)
4227 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4237 unsigned Rt = Inst.getOperand(1).getReg();
4239 if (Rt == Rt2)
4240 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4253 unsigned Rt = Inst.getOperand(1).getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 5813 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5816 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt
7415 unsigned Rt = MRI->getEncodingValue(Reg1);
7418 // Rt2 must be Rt + 1 and Rt must be even.
7419 if (Rt + 1 != Rt2 || (Rt & 1)) {
7536 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
7540 // Rt can't be R14.
7541 if (Rt == 14
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 1918 enum arm_reg_type rt; local
1921 rt = REG_TYPE_RN;
1923 rt = REG_TYPE_PSEUDO;
1925 reg = arm_reg_parse (&str, rt);
6672 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6679 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6842 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6902 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
7957 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
9956 unsigned Rt = inst.operands[0].reg
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 1917 enum arm_reg_type rt; local
1920 rt = REG_TYPE_RN;
1922 rt = REG_TYPE_PSEUDO;
1924 reg = arm_reg_parse (&str, rt);
6675 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6682 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6845 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6905 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
7960 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
9959 unsigned Rt = inst.operands[0].reg
[all...] |
