| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 3680 /* The IMM field in an SE_IM5 instruction. */
4391 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
4392 #define SE_IM5(op, xop) \
4395 #define SE_IM5_MASK SE_IM5(0x3f, 1)
10205 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10206 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10207 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10208 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10209 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10210 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 3680 /* The IMM field in an SE_IM5 instruction. */
4390 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
4391 #define SE_IM5(op, xop) \
4394 #define SE_IM5_MASK SE_IM5(0x3f, 1)
10140 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10141 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10142 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10143 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10144 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10145 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 3602 /* The IMM field in an SE_IM5 instruction. */
4300 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
4301 #define SE_IM5(op, xop) \
4304 #define SE_IM5_MASK SE_IM5(0x3f, 1)
9997 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9998 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9999 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10000 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
10001 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
10002 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 3602 /* The IMM field in an SE_IM5 instruction. */
4300 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
4301 #define SE_IM5(op, xop) \
4304 #define SE_IM5_MASK SE_IM5(0x3f, 1)
9986 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9987 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9988 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9989 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
9990 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
9991 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}
[all...] |
