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    Searched defs:SF (Results 1 - 23 of 23) sorted by relevancy

  /src/external/mit/isl/dist/
isl_map_lexopt_templ.c 18 #define SF(TYPE,SUFFIX) xSF(TYPE,SUFFIX)
31 static __isl_give TYPE *SF(isl_basic_map_partial_lexopt,SUFFIX)(
35 return SF(isl_tab_basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty,
39 __isl_give TYPE *SF(isl_basic_map_partial_lexmax,SUFFIX)(
44 return SF(isl_basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty, flags);
47 __isl_give TYPE *SF(isl_basic_map_partial_lexmin,SUFFIX)(
52 return SF(isl_basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty, flags);
55 __isl_give TYPE *SF(isl_basic_set_partial_lexmin,SUFFIX)(
59 return SF(isl_basic_map_partial_lexmin,SUFFIX)(bset, dom, empty);
62 __isl_give TYPE *SF(isl_basic_set_partial_lexmax,SUFFIX)
    [all...]
isl_tab_lexopt_templ.c 15 #define SF(TYPE,SUFFIX) xSF(TYPE,SUFFIX)
49 static TYPE *SF(basic_map_partial_lexopt_symm,SUFFIX)(
127 return SF(basic_map_partial_lexopt_symm_core,SUFFIX)(bmap, dom, empty,
149 static __isl_give TYPE *SF(basic_map_partial_lexopt,SUFFIX)(
164 return SF(basic_map_partial_lexopt_base,SUFFIX)(bmap, dom,
167 return SF(basic_map_partial_lexopt_symm,SUFFIX)(bmap, dom, empty, max,
199 __isl_give TYPE *SF(isl_tab_basic_map_partial_lexopt,SUFFIX)(
221 return SF(basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty,
230 return SF(basic_map_partial_lexopt,SUFFIX)(bmap, dom, empty, max);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
dcn20_vmid.h 43 #define SF(reg_name, field_name, post_fix)\
56 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
57 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
58 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
59 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
60 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
61 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
62 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
63 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
dcn20_mmhubbub.h 57 #define SF(reg_name, field_name, post_fix)\
120 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
122 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
123 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
124 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
125 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
126 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
127 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
128 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),
    [all...]
dcn20_dwb.h 55 #define SF(reg_name, field_name, post_fix)\
108 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
109 SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
110 SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
111 SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
113 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
114 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
115 SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
116 SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_factory_dcn20.c 74 #define SF(reg_name, field_name, post_fix)\
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
amdgpu_hw_factory_dcn21.c 72 #define SF(reg_name, field_name, post_fix)\
  /src/external/bsd/pcc/dist/pcc/mip/
softfloat.h 44 typedef struct softfloat SF;
45 SF soft_neg(SF);
46 SF soft_cast(CONSZ v, TWORD);
47 SF soft_plus(SF, SF);
48 SF soft_minus(SF, SF);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_audio.h 46 #define SF(reg_name, field_name, post_fix)\
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
55 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
56 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
58 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
59 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),
    [all...]
  /src/bin/pax/
options.h 70 #define SF 0x000001000ULL
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_dwb.h 51 #define SF(reg_name, field_name, post_fix)\
89 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
91 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
92 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
93 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
94 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
95 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
96 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
97 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/ExecutionEngine/Interpreter/
Execution.cpp 41 static void SetValue(Value *V, GenericValue Val, ExecutionContext &SF) {
42 SF.Values[V] = Val;
63 ExecutionContext &SF = ECStack.back();
65 GenericValue Src = getOperandValue(I.getOperand(0), SF);
96 SetValue(&I, R, SF);
333 ExecutionContext &SF = ECStack.back();
335 GenericValue Src1 = getOperandValue(I.getOperand(0), SF);
336 GenericValue Src2 = getOperandValue(I.getOperand(1), SF);
355 SetValue(&I, R, SF);
666 ExecutionContext &SF = ECStack.back()
    [all...]
  /src/sys/arch/sh3/sh3/
db_interface.c 584 struct switchframe *sf = &curpcb->pcb_sf; local
590 #define SF(x) db_printf("sf_" #x "\t\t0x%08x\t", sf->sf_ ## x); \
591 __db_print_symbol(sf->sf_ ## x)
593 SF(sr);
594 SF(pr);
595 SF(gbr);
596 SF(r8);
597 SF(r9);
598 SF(r10)
    [all...]
  /src/usr.sbin/lpr/common_source/
common.c 103 long SF; /* suppress FF on each print job */
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
ExprEngineCallAndReturn.cpp 80 const StackFrameContext *SF = Node->getStackFrame();
87 if (PP.getStackFrame() == SF) {
111 if (CE->getCalleeContext() == SF)
  /src/external/apache2/llvm/dist/llvm/lib/MC/
MCAssembler.cpp 674 const MCSymbolIdFragment &SF = cast<MCSymbolIdFragment>(F);
675 support::endian::write<uint32_t>(OS, SF.getSymbol()->getIndex(), Endian);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 690 MachineOperand &SF = MI.getOperand(3);
691 if (ST.isReg() && SF.isReg()) {
693 if (RT == RegisterRef(SF)) {
712 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true);
  /src/external/gpl3/binutils/dist/opcodes/
mips-opc.c 347 #define SF (ALX \
669 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF },
679 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
801 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
808 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
815 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
825 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
832 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
839 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
846 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
mips-opc.c 347 #define SF (ALX \
669 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF },
679 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
801 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
808 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
815 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
825 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
832 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
839 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
846 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }
    [all...]
  /src/external/gpl3/gdb/dist/sim/common/
cgen-fpu.h 13 typedef USI SF;
66 /* basic SF ops */
68 SF (*addsf) (CGEN_FPU*, SF, SF);
69 SF (*subsf) (CGEN_FPU*, SF, SF);
70 SF (*mulsf) (CGEN_FPU*, SF, SF)
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/common/
cgen-fpu.h 13 typedef USI SF;
66 /* basic SF ops */
68 SF (*addsf) (CGEN_FPU*, SF, SF);
69 SF (*subsf) (CGEN_FPU*, SF, SF);
70 SF (*mulsf) (CGEN_FPU*, SF, SF)
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
mips-opc.c 347 #define SF (ALX \
669 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF },
679 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
801 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
808 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
815 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
825 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
832 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
839 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
846 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
mips-opc.c 347 #define SF (ALX \
669 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF },
679 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
801 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
808 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
815 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
825 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
832 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
839 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
846 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }
    [all...]

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