1 /* $NetBSD: pci_machdep.c,v 1.84 2025/10/04 15:32:43 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * functions expected by the MI PCI code. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.84 2025/10/04 15:32:43 thorpej Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/device.h> 42 43 #define _SPARC_BUS_DMA_PRIVATE 44 #include <sys/bus.h> 45 #include <machine/autoconf.h> 46 #include <machine/openfirm.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pci_calls.h> 50 51 #include <dev/ofw/ofw_pci.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/sparc64/cache.h> 55 56 #include "locators.h" 57 58 #ifdef DEBUG 59 #define SPDB_CONF 0x01 60 #define SPDB_INTR 0x04 61 #define SPDB_INTMAP 0x08 62 #define SPDB_PROBE 0x20 63 #define SPDB_TAG 0x40 64 int sparc_pci_debug = 0x0; 65 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 66 #else 67 #define DPRINTF(l, s) 68 #endif 69 70 /* this is a base to be copied */ 71 struct sparc_pci_chipset _sparc_pci_chipset = { 72 .cookie = NULL, 73 }; 74 75 static pcitag_t 76 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 77 { 78 pcitag_t tag; 79 pcireg_t reg; 80 81 tag = PCITAG_CREATE(node, b, d, f); 82 83 DPRINTF(SPDB_TAG, 84 ("%s: creating tag for node %x bus %d dev %d fn %d\n", 85 __func__, node, b, d, f)); 86 87 /* Enable all the different spaces for this device */ 88 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 89 reg |= PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 90 PCI_COMMAND_IO_ENABLE; 91 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 92 93 return (tag); 94 } 95 96 static int 97 sparc64_pci_bus_get_child_devhandle(device_t dev, devhandle_t call_handle, 98 void *v) 99 { 100 struct pci_bus_get_child_devhandle_args *args = v; 101 102 /* 103 * We've already gone through the trouble of encoding the 104 * OF phandle into the pcitag_t. 105 */ 106 int node = PCITAG_NODE(args->tag); 107 if (node != -1) { 108 args->devhandle = devhandle_from_of(call_handle, node); 109 return 0; 110 } 111 112 return ENODEV; 113 } 114 OF_DEVICE_CALL_REGISTER(PCI_BUS_GET_CHILD_DEVHANDLE_STR, 115 sparc64_pci_bus_get_child_devhandle) 116 117 /* 118 * functions provided to the MI code. 119 */ 120 121 void 122 pci_attach_hook(device_t parent, device_t self, 123 struct pcibus_attach_args *pba) 124 { 125 } 126 127 int 128 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 129 { 130 131 return 32; 132 } 133 134 pcitag_t 135 pci_make_tag(pci_chipset_tag_t pc, int b, int d, int f) 136 { 137 struct ofw_pci_register reg; 138 pcitag_t tag; 139 int (*valid)(void *); 140 int node, new_node, len; 141 #ifdef DEBUG 142 char name[80]; 143 memset(name, 0, sizeof(name)); 144 #endif 145 146 /* 147 * Refer to the PCI/CardBus bus node first. 148 * It returns a tag if node is present and bus is valid. 149 */ 150 if (0 <= b && b < 256) { 151 KASSERT(pc->spc_busnode != NULL); 152 node = (*pc->spc_busnode)[b].node; 153 valid = (*pc->spc_busnode)[b].valid; 154 if (node != 0 && d == 0 && 155 (valid == NULL || (*valid)((*pc->spc_busnode)[b].arg))) 156 return ofpci_make_tag(pc, node, b, d, f); 157 } 158 159 /* 160 * Hunt for the node that corresponds to this device 161 * 162 * We could cache this info in an array in the parent 163 * device... except then we have problems with devices 164 * attached below pci-pci bridges, and we would need to 165 * add special code to the pci-pci bridge to cache this 166 * info. 167 */ 168 169 tag = PCITAG_CREATE(-1, b, d, f); 170 node = pc->rootnode; 171 /* 172 * First make sure we're on the right bus. If our parent 173 * has a bus-range property and we're not in the range, 174 * then we're obviously on the wrong bus. So go up one 175 * level. 176 */ 177 DPRINTF(SPDB_PROBE, ("curnode %x %s\n", node, 178 prom_getpropstringA(node, "name", name, sizeof(name)))); 179 #if 0 180 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 181 sizeof(busrange)) == sizeof(busrange)) && 182 (b < busrange[0] || b > busrange[1])) { 183 /* Out of range, go up one */ 184 node = OF_parent(node); 185 DPRINTF(SPDB_PROBE, printf("going up to node %x %s\n", 186 node, 187 prom_getpropstringA(node, "name", name, sizeof(name)))); 188 } 189 #endif 190 node = prom_firstchild(node); 191 /* 192 * Now traverse all peers until we find the node or we find 193 * the right bridge. 194 * 195 * XXX We go up one and down one to make sure nobody's missed. 196 * but this should not be necessary. 197 */ 198 for (node = ((node)); node; node = prom_nextsibling(node)) { 199 200 DPRINTF(SPDB_PROBE, ("checking node %x %s\n", node, 201 prom_getpropstringA(node, "name", name, sizeof(name)))); 202 203 #if 1 204 /* 205 * Check for PCI-PCI bridges. If the device we want is 206 * in the bus-range for that bridge, work our way down. 207 */ 208 while (1) { 209 int busrange[2], *brp; 210 len = 2; 211 brp = busrange; 212 if (prom_getprop(node, "bus-range", sizeof(*brp), 213 &len, &brp) != 0) 214 break; 215 if (len != 2 || b < busrange[0] || b > busrange[1]) 216 break; 217 /* Go down 1 level, as long as we're able */ 218 new_node = prom_firstchild(node); 219 if (new_node == 0) 220 break; 221 node = new_node; 222 DPRINTF(SPDB_PROBE, ("going down to node %x %s\n", node, 223 prom_getpropstringA(node, "name", name, 224 sizeof(name)))); 225 } 226 #endif /*1*/ 227 /* 228 * We only really need the first `reg' property. 229 * 230 * For simplicity, we'll query the `reg' when we 231 * need it. Otherwise we could malloc() it, but 232 * that gets more complicated. 233 */ 234 len = prom_getproplen(node, "reg"); 235 if (len < sizeof(reg)) 236 continue; 237 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 238 panic("pci_probe_bus: OF_getprop len botch"); 239 240 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 241 continue; 242 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 243 continue; 244 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 245 continue; 246 247 /* Got a match */ 248 tag = ofpci_make_tag(pc, node, b, d, f); 249 250 return (tag); 251 } 252 /* No device found -- return a dead tag */ 253 return (tag); 254 } 255 256 void 257 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 258 { 259 260 if (bp != NULL) 261 *bp = PCITAG_BUS(tag); 262 if (dp != NULL) 263 *dp = PCITAG_DEV(tag); 264 if (fp != NULL) 265 *fp = PCITAG_FUN(tag); 266 } 267 268 int 269 sparc64_pci_enumerate_bus1(struct pci_softc *sc, const int *locators, 270 int (*match)(void *, const struct pci_attach_args *), void *cookie, 271 struct pci_attach_args *pap) 272 { 273 struct ofw_pci_register reg; 274 pci_chipset_tag_t pc = sc->sc_pc; 275 pcitag_t tag; 276 pcireg_t class, csr, bhlc, ic; 277 int node, b, d, f, ret; 278 int bus_frequency, lt, cl, cacheline; 279 char name[30]; 280 #if 0 281 extern int pci_config_dump; 282 #endif 283 284 if (sc->sc_bridgetag) 285 node = PCITAG_NODE(*sc->sc_bridgetag); 286 else 287 node = pc->rootnode; 288 289 bus_frequency = 290 prom_getpropint(node, "clock-frequency", 33000000) / 1000000; 291 292 /* 293 * Make sure the cache line size is at least as big as the 294 * ecache line and the streaming cache (64 byte). 295 */ 296 cacheline = uimax(ecache_min_line_size, 64); 297 KASSERT((cacheline/64)*64 == cacheline && 298 (cacheline/ecache_min_line_size)*ecache_min_line_size == cacheline && 299 (cacheline/4)*4 == cacheline); 300 301 #if 0 302 /* 303 * XXX this faults on Fire PCIe controllers. 304 * XXX move into the psycho and schizo driver front ends. 305 */ 306 /* Turn on parity for the bus. */ 307 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 308 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 309 csr |= PCI_COMMAND_PARITY_ENABLE; 310 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 311 312 /* 313 * Initialize the latency timer register. 314 * The value 0x40 is from Solaris. 315 */ 316 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 317 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 318 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 319 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 320 321 if (pci_config_dump) 322 pci_conf_print(pc, tag, NULL); 323 #endif 324 325 for (node = prom_firstchild(node); node != 0 && node != -1; 326 node = prom_nextsibling(node)) { 327 name[0] = name[29] = 0; 328 prom_getpropstringA(node, "name", name, sizeof(name)); 329 330 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 331 sizeof(class)) 332 continue; 333 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) { 334 panic("pci_enumerate_bus1: \"%s\" regs too small", 335 name); 336 } 337 338 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 339 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 340 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 341 342 if (sc->sc_bus != b) { 343 aprint_error_dev(sc->sc_dev, "WARNING: incorrect " 344 "bus # for \"%s\" (%d/%d/%d)\n", name, b, d, f); 345 continue; 346 } 347 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 348 (locators[PCICF_DEV] != d)) 349 continue; 350 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) && 351 (locators[PCICF_FUNCTION] != f)) 352 continue; 353 354 tag = ofpci_make_tag(pc, node, b, d, f); 355 356 /* 357 * Turn on parity and fast-back-to-back for the device. 358 */ 359 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 360 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 361 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 362 csr |= PCI_COMMAND_PARITY_ENABLE; 363 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 364 365 /* 366 * Initialize the latency timer register for busmaster 367 * devices to work properly. 368 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 369 * Also initialize the cache line size register. 370 * Solaris anytime sets this register to the value 0x10. 371 */ 372 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 373 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 374 375 lt = uimin(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 376 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 377 lt = PCI_LATTIMER(bhlc); 378 379 cl = PCI_CACHELINE(bhlc); 380 if (cl == 0) 381 cl = cacheline; 382 383 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 384 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 385 bhlc |= (lt << PCI_LATTIMER_SHIFT) | 386 (cl << PCI_CACHELINE_SHIFT); 387 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 388 389 ret = pci_probe_device1(sc, tag, match, cookie, pap); 390 if (match != NULL && ret != 0) 391 return (ret); 392 } 393 return (0); 394 } 395 396 const char * 397 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 398 size_t len) 399 { 400 snprintf(buf, len, "ivec %x", ih); 401 DPRINTF(SPDB_INTR, ("pci_intr_string: returning %s\n", buf)); 402 403 return buf; 404 } 405 406 const struct evcnt * 407 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 408 { 409 410 /* XXX for now, no evcnt parent reported */ 411 return NULL; 412 } 413 414 int 415 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 416 int attr, uint64_t data) 417 { 418 419 switch (attr) { 420 case PCI_INTR_MPSAFE: 421 return 0; 422 default: 423 return ENODEV; 424 } 425 } 426 427 /* 428 * interrupt mapping foo. 429 * XXX: how does this deal with multiple interrupts for a device? 430 */ 431 int 432 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 433 { 434 pcitag_t tag = pa->pa_tag; 435 int interrupts[4], *intp, int_used; 436 int len, node = PCITAG_NODE(tag); 437 char devtype[30]; 438 439 intp = &interrupts[0]; 440 len = prom_getproplen(node, "interrupts"); 441 if (len > sizeof(interrupts)) { 442 DPRINTF(SPDB_INTMAP, 443 ("pci_intr_map: too many available interrupts\n")); 444 return (ENODEV); 445 } 446 if (prom_getprop(node, "interrupts", len, 447 &len, &intp) != 0 || len != 1) { 448 DPRINTF(SPDB_INTMAP, 449 ("pci_intr_map: could not read interrupts\n")); 450 return (ENODEV); 451 } 452 453 /* XXX We pick the first interrupt, but should do better */ 454 int_used = interrupts[0]; 455 if (OF_mapintr(node, &int_used, sizeof(int_used), 456 sizeof(int_used)) < 0) { 457 printf("OF_mapintr failed\n"); 458 if (pa->pa_pc->spc_find_ino) 459 pa->pa_pc->spc_find_ino(pa, &int_used); 460 } 461 DPRINTF(SPDB_INTMAP, ("OF_mapintr() gave %x\n", int_used)); 462 463 /* Try to find an IPL for this type of device. */ 464 prom_getpropstringA(node, "device_type", devtype, sizeof(devtype)); 465 for (len = 0; intrmap[len].in_class != NULL; len++) 466 if (strcmp(intrmap[len].in_class, devtype) == 0) { 467 int_used |= INTLEVENCODE(intrmap[len].in_lev); 468 DPRINTF(SPDB_INTMAP, ("reset to %x\n", int_used)); 469 break; 470 } 471 472 *ihp = int_used; 473 474 /* Call the sub-driver is necessary */ 475 if (pa->pa_pc->spc_intr_map) 476 (*pa->pa_pc->spc_intr_map)(pa, ihp); 477 478 return (0); 479 } 480 481 void 482 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 483 { 484 485 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 486 487 /* XXX */ 488 /* panic("can't disestablish PCI interrupts yet"); */ 489 } 490 491 int 492 sparc_pci_childspace(int type) 493 { 494 int ss; 495 496 switch (type) { 497 case PCI_CONFIG_BUS_SPACE: 498 ss = 0x00; 499 break; 500 case PCI_IO_BUS_SPACE: 501 ss = 0x01; 502 break; 503 case PCI_MEMORY_BUS_SPACE: 504 ss = 0x02; 505 break; 506 #if 0 507 /* we don't do 64 bit memory space */ 508 case PCI_MEMORY64_BUS_SPACE: 509 ss = 0x03; 510 break; 511 #endif 512 default: 513 panic("get_childspace: unknown bus type: %d", type); 514 } 515 516 return (ss); 517 } 518
Indexes created Wed Oct 15 16:09:53 GMT 2025