1 /* $NetBSD: spr.h,v 1.1 2012/07/17 20:46:07 matt Exp $ */ 2 3 #ifndef _POWERPC_MPC8XX_SPR_H_ 4 #define _POWERPC_MPC8XX_SPR_H_ 5 6 /* 7 * Process Version for MPC8xx 8 */ 9 10 #define MPC860 0x0050 11 12 /* 13 * Special Purpose Register declarations for MPC8xx 14 */ 15 16 #define SPR_DSISR 0x012 /* .68 DSI exception source */ 17 #define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 18 #define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 19 #define DSISR_STORE 0x02000000 /* Store operation */ 20 #define SPR_DAR 0x013 /* .68 Data Address Register */ 21 #define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ 22 #define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ 23 #define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ 24 25 #define SPR_CMPA 0x090 26 #define SPR_CMPB 0x091 27 #define SPR_CMPC 0x092 28 #define SPR_CMPD 0x093 29 #define SPR_ICR 0x094 30 #define SPR_DER 0x095 31 #define SPR_COUNTA 0x096 32 #define SPR_COUNTB 0x097 33 #define SPR_CMPE 0x098 34 #define SPR_CMPF 0x099 35 #define SPR_CMPG 0x09a 36 #define SPR_CMPH 0x09b 37 #define SPR_LCTRL1 0x09c 38 #define SPR_LCTRL2 0x09d 39 #define SPR_ICTRL 0x09e 40 #define SPR_BAR 0x09f 41 42 #define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */ 43 #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ 44 #define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ 45 #define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ 46 #define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ 47 #define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ 48 #define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ 49 #define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ 50 #define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ 51 #define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ 52 #define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ 53 #define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ 54 #define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ 55 #define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ 56 #define SPR_DC_CST 0x238 /* ..8 Data Cache CSR */ 57 #define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ 58 #define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ 59 #define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ 60 #define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ 61 #define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ 62 #define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ 63 #define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ 64 #define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ 65 #define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ 66 #define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ 67 #define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ 68 #define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ 69 #define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ 70 #define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ 71 #define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ 72 #define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ 73 #define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ 74 #define SPR_DC_ADR 0x239 /* ..8 Data Cache Address */ 75 #define SPR_DC_DAT 0x23a /* ..8 Data Cache Data */ 76 #define SPR_DPIR 0x275 /* ,,8 */ 77 #define SPR_DPDR 0x276 /* ,,8 */ 78 #define SPR_IMMR 0x275 /* ,,8 Internal Memoru Map */ 79 #define IMMR_ISB 0xffff0000 /* Internal Space Base */ 80 #define IMMR_PARTNUM 0x0000ff00 /* Part Number (RO) */ 81 #define IMMR_MASKNUM 0x000000ff /* Mask Number (R0) */ 82 #define SPR_MI_CTR 0x310 /* ..8 IMMU control */ 83 #define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ 84 #define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ 85 #define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ 86 #define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ 87 #define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ 88 #define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ 89 #define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ 90 #define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ 91 #define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ 92 #define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ 93 #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ 94 #define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ 95 #define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ 96 #define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ 97 #define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ 98 #define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ 99 #define Mx_EPN_EV 0x00000020 /* Entry Valid */ 100 #define Mx_EPN_ASID 0x0000000f /* Address Space ID */ 101 #define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ 102 #define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ 103 #define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ 104 #define Mx_TWC_G 0x00000010 /* Guarded memory */ 105 #define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ 106 #define MD_TWC_WT 0x00000002 /* Write-Through */ 107 #define Mx_TWC_V 0x00000001 /* Entry Valid */ 108 #define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ 109 #define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ 110 #define Mx_RPN_PP 0x00000ff0 /* Page Protection */ 111 #define Mx_RPN_SPS 0x00000008 /* Small Page Size */ 112 #define Mx_RPN_SH 0x00000004 /* SHared page */ 113 #define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ 114 #define Mx_RPN_V 0x00000001 /* Valid */ 115 #define SPR_MD_CTR 0x318 /* ..8 DMMU control */ 116 #define SPR_M_CASID 0x319 /* ..8 CASID */ 117 #define M_CASID 0x0000000f /* Current AS ID */ 118 #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ 119 #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ 120 #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ 121 #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ 122 #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ 123 #define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ 124 #define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ 125 #define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ 126 #define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ 127 #define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ 128 #define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ 129 #define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ 130 #define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ 131 #define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ 132 133 #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ 134 #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ 135 #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ 136 #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ 137 #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ 138 #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ 139 #define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ 140 #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 141 #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 142 #define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 143 #define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 144 145 #endif /* !_POWERPC_MPC8XX_SPR_H_ */ 146
Indexes created Mon Sep 22 13:09:51 GMT 2025