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Searched defs:SR1 (Results 1 - 25 of 25) sorted by relevancy

/src/external/bsd/jemalloc/dist/test/include/test/
SFMT-params11213.h	`42 #define SR1 7 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params1279.h	`42 #define SR1 5 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params132049.h	`42 #define SR1 21 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params19937.h	`42 #define SR1 11 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params216091.h	`42 #define SR1 10 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params2281.h	`42 #define SR1 5 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params4253.h	`42 #define SR1 7 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params44497.h	`42 #define SR1 9 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params607.h	`42 #define SR1 13 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params86243.h	`42 #define SR1 19 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
/src/external/bsd/jemalloc.old/dist/test/include/test/
SFMT-params11213.h	`42 #define SR1 7 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params1279.h	`42 #define SR1 5 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params132049.h	`42 #define SR1 21 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params19937.h	`42 #define SR1 11 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params216091.h	`42 #define SR1 10 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params2281.h	`42 #define SR1 5 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params4253.h	`42 #define SR1 7 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params44497.h	`42 #define SR1 9 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params607.h	`42 #define SR1 13 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
SFMT-params86243.h	`42 #define SR1 19 57 #define ALTI_SR1 (vector unsigned int)(SR1, SR1, SR1, SR1) 71 #define ALTI_SR1 {SR1, SR1, SR1, SR1}`
/src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonGenMux.cpp	`300 // SR1, SR2 - source registers from the first and the second definition. 306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); 315 if (CanDown && DU.Defs[SR1])`
/src/external/gpl3/binutils/dist/opcodes/
v850-opc.c	1041 #define SR1 (OLDSR1 + 1) 1045 #define OLDSR2 (SR1 + 1) 1755 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1756 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1760 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1761 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1765 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1766 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
/src/external/gpl3/binutils.old/dist/opcodes/
v850-opc.c	1041 #define SR1 (OLDSR1 + 1) 1045 #define OLDSR2 (SR1 + 1) 1755 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1756 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1760 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1761 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1765 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1766 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
/src/external/gpl3/gdb/dist/opcodes/
v850-opc.c	1041 #define SR1 (OLDSR1 + 1) 1045 #define OLDSR2 (SR1 + 1) 1755 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1756 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1760 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1761 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1765 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1766 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
/src/external/gpl3/gdb.old/dist/opcodes/
v850-opc.c	1041 #define SR1 (OLDSR1 + 1) 1045 #define OLDSR2 (SR1 + 1) 1755 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1756 { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1760 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1761 { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, 1765 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, 1766 { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },

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