| /src/external/bsd/jemalloc/dist/test/include/test/ |
| SFMT-params11213.h | 43 #define SR2 3
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| SFMT-params1279.h | 43 #define SR2 1
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| SFMT-params132049.h | 43 #define SR2 1
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| SFMT-params19937.h | 43 #define SR2 1
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| SFMT-params216091.h | 43 #define SR2 1
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| SFMT-params2281.h | 43 #define SR2 1
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| SFMT-params4253.h | 43 #define SR2 1
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| SFMT-params44497.h | 43 #define SR2 3
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| SFMT-params607.h | 43 #define SR2 3
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| SFMT-params86243.h | 43 #define SR2 1
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| /src/external/bsd/jemalloc.old/dist/test/include/test/ |
| SFMT-params11213.h | 43 #define SR2 3
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| SFMT-params1279.h | 43 #define SR2 1
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| SFMT-params132049.h | 43 #define SR2 1
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| SFMT-params19937.h | 43 #define SR2 1
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| SFMT-params216091.h | 43 #define SR2 1
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| SFMT-params2281.h | 43 #define SR2 1
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| SFMT-params4253.h | 43 #define SR2 1
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| SFMT-params44497.h | 43 #define SR2 3
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| SFMT-params607.h | 43 #define SR2 3
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| SFMT-params86243.h | 43 #define SR2 1
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonGenMux.cpp | 300 // SR1, SR2 - source registers from the first and the second definition.
307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register();
317 if (CanUp && DU.Defs[SR2])
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| /src/external/gpl3/binutils/dist/opcodes/ |
| v850-opc.c | 1048 #define SR2 (OLDSR2 + 1)
1052 #define FFF (SR2 + 1)
1599 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1600 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1604 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1605 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1610 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1611 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
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| /src/external/gpl3/binutils.old/dist/opcodes/ |
| v850-opc.c | 1048 #define SR2 (OLDSR2 + 1)
1052 #define FFF (SR2 + 1)
1599 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1600 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1604 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1605 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1610 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1611 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| v850-opc.c | 1048 #define SR2 (OLDSR2 + 1)
1052 #define FFF (SR2 + 1)
1599 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1600 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1604 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1605 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1610 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1611 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| v850-opc.c | 1048 #define SR2 (OLDSR2 + 1)
1052 #define FFF (SR2 + 1)
1599 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1600 { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1604 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1605 { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1610 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1611 { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
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