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    Searched defs:SRA (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiAluCode.h 37 SRA = 0x37,
96 case SRA:
114 .Case("sha", SRA)
138 case ISD::SRA:
139 return AluCode::SRA;
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZSelectionDAGInfo.cpp 175 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL,
177 return SRA;
  /src/usr.sbin/gspa/gspa/
gsp_inst.c 74 #define SRA (KREG|IMMNEG)
240 {"SRA", 0x2800, SRA, {EXREG, REG, 0, 0}},
241 {"SRL", 0x2C00, SRA, {EXREG, REG, 0, 0}},
  /src/external/lgpl3/gmp/dist/demos/
pexpr.c 95 AND, IOR, XOR, SLL, SRA, POPCNT, HAMDIST, GCD, LCM, SQRT, ROOT, FAC,
  /src/sys/external/bsd/sljit/dist/sljit_src/
sljitNativeMIPS_common.c 166 #define SRA (HI(0) | LO(3))
sljitNativeSPARC_common.c 158 #define SRA (OPC1(0x2) | OPC3(0x27))
805 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(SLJIT_R0) | IMM(31), DR(TMP_REG1)));
  /src/external/gpl3/gdb/dist/sim/erc32/
exec.c 154 #define SRA 0x27
1023 case SRA:
  /src/external/gpl3/gdb.old/dist/sim/erc32/
exec.c 154 #define SRA 0x27
1023 case SRA:
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 648 SRA,
732 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 1371 if (Opc == ISD::SRA)
1650 case ISD::SRA: return visitSRA(N);
1777 case ISD::SRA:
2235 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2238 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
3281 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3284 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3503 // fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
3505 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 1150 setOperationAction(ISD::SRA, VT, Custom);
1382 setOperationAction(ISD::SRA, VT, Custom);
1504 setOperationAction(ISD::SRA, VT, Custom);
2772 if (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA)
2974 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
3002 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
4583 case ISD::SRA:
7003 DAG.getNode(ISD::SRA, dl, VT, LHS,
10380 case ISD::SRA:
10383 unsigned Opc = Op.getOpcode() == ISD::SRA ? AArch64ISD::SRA_PRE
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 193 setOperationAction(ISD::SRA, VT, Custom);
266 setOperationAction(ISD::SRA, VT, Custom);
961 setTargetDAGCombine(ISD::SRA);
1131 setOperationAction(ISD::SRA, MVT::i64, Custom);
1138 // assuming that ISD::SRL and SRA of i64 are already marked custom
1909 if (Op.getOpcode() != ISD::SRA)
1924 // Check for a signed 16-bit value. We special case SRA because it makes it
3890 SDValue SRA =
3891 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3892 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand)
    [all...]

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