| /src/sbin/dmctl/ |
| Makefile | 4 SRC= dmctl.c
|
| /src/tests/lib/libc/atomic/ |
| t___sync_add.c | 48 #define SRC (0xf0e0d0c0b0a09081UL)
60 TYPE src; \
65 src = (TYPE)SRC; \
68 res = NAME(&val, src); \
91 TYPE src; \
95 src = (TYPE)SRC; \
97 res = NAME(&val, src); \
|
| t___sync_and.c | 48 #define SRC (0xf0f0f0f0f0f0f0f0UL)
60 TYPE src; \
65 src = (TYPE)SRC; \
68 res = NAME(&val, src); \
91 TYPE src; \
95 src = (TYPE)SRC; \
97 res = NAME(&val, src); \
|
| t___sync_nand.c | 48 #define SRC (0xf0f0f0f0f0f0f0f0UL)
60 TYPE src; \
65 src = (TYPE)SRC; \
68 res = NAME(&val, src); \
91 TYPE src; \
95 src = (TYPE)SRC; \
97 res = NAME(&val, src); \
|
| t___sync_or.c | 48 #define SRC (0xf0f0f0f0f0f0f0f0UL)
60 TYPE src; \
65 src = (TYPE)SRC; \
68 res = NAME(&val, src); \
91 TYPE src; \
95 src = (TYPE)SRC; \
97 res = NAME(&val, src); \
|
| t___sync_sub.c | 48 #define SRC (0x1122334455667787UL)
60 TYPE src; \
65 src = (TYPE)SRC; \
68 res = NAME(&val, src); \
91 TYPE src; \
95 src = (TYPE)SRC; \
97 res = NAME(&val, src); \
|
| t___sync_xor.c | 48 #define SRC (0xf0f0f0f0f0f0f0f0UL)
60 TYPE src; \
65 src = (TYPE)SRC; \
68 res = NAME(&val, src); \
91 TYPE src; \
95 src = (TYPE)SRC; \
97 res = NAME(&val, src); \
|
| t_atomic_add.c | 40 #define SRC (0xf0e0d0c0b0a09081UL)
55 STYPE src; \
58 src = (STYPE)SRC; \
60 NAME(&val, src); \
85 STYPE src; \
89 src = (STYPE)SRC; \
91 res = NAME(&val, src); \
|
| t_atomic_and.c | 40 #define SRC (0xf0f0f0f0f0f0f0f0UL)
55 TYPE src; \
58 src = (TYPE)SRC; \
60 NAME(&val, src); \
84 TYPE src; \
88 src = (TYPE)SRC; \
90 res = NAME(&val, src); \
|
| t_atomic_or.c | 40 #define SRC (0xf0f0f0f0f0f0f0f0UL)
55 TYPE src; \
58 src = (TYPE)SRC; \
60 NAME(&val, src); \
84 TYPE src; \
88 src = (TYPE)SRC; \
90 res = NAME(&val, src); \
|
| /src/external/gpl2/gettext/dist/os2/ |
| Makefile | 50 INCLUDE = -I. -I$(ROOT) -I$(ROOT)intl -I$(ROOT)src -I$(ROOT)lib -I$(ROOT)libuniname
105 $(shell sed $(ROOT)src/Makefile.am -ne "/^bin_PROGRAMS =/,/[^\]$$/p"))))
107 SRC.SOURCES = $(filter-out $(addprefix $(ROOT)src/,$(PROGRAMS:.exe=.c)),\
108 $(wildcard $(ROOT)src/*.c))
109 SRC.OBJECTS = $(addprefix $(OUT),$(subst $(ROOT),,$(SRC.SOURCES:.c=.o)))
125 OUTDIRS = $(OUT) $(sort $(dir $(INTL.OBJECTS) $(SRC.OBJECTS) $(LIB.OBJECTS) \
146 # instead a library containing all the object files from src directory, and
149 $(OUT)%.exe: $(OUT)src/%.o $(OUT)util.a $(OUT)uniname.a $(LINKINTL
[all...] |
| /src/common/lib/libc/arch/aarch64/string/ |
| bcopy.S | 38 * void *memcpy(void * restrict dst, const void * restrict src, size_t len);
49 * void *memmove(void *dst, const void *src, size_t len);
60 * void bcopy(const void *src, void *dst, size_t len);
76 #define SRC x7
82 #define SRC_ALIGNBIT x11 /* (SRC & 7) * 8 */
106 /* if (len & 4) { *--(uint32_t *)dst = *--(uint32_t *)src; } */
111 /* if (len & 2) { *--(uint16_t *)dst = *--(uint16_t *)src; } */
116 /* if (len & 1) { *--(uint8_t *)dst = *--(uint8_t *)src; } */
128 /* *--(uint64_t *)dst = *--(uint64_t *)src; */
131 /* if (len & 4) { *--(uint32_t *)dst = *--(uint32_t *)src; } */
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MachineSink.cpp | 278 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
280 if (SRC != DRC)
|
| MachineVerifier.cpp | 960 Register Src = MI->getOperand(1).getReg();
961 LLT SrcTy = MRI->getType(Src);
973 if (MRI->getRegBankOrNull(Src) != MRI->getRegBankOrNull(Dst)) {
980 if (MRI->getRegClassOrNull(Src) != MRI->getRegClassOrNull(Dst))
1369 report("G_BRJT src operand 0 must be a pointer type", MI);
1372 report("G_BRJT src operand 1 must be a jump table index", MI);
1376 report("G_BRJT src operand 2 must be a scalar reg type", MI);
1385 report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1470 report("src operand 1 must be a scalar reg type", MI);
1475 report("src operand 2 must be an immediate type", MI)
[all...] |
| /src/external/gpl3/binutils/dist/include/opcode/ |
| tic54x.h | 49 OP_SRC1, /* src accumulator in bit 8 */
50 OP_SRC, /* src accumulator in bit 9 */
100 #define SRC(OP) ((OP)&0x200)
|
| h8300.h | 101 SRC = 0x10000,
127 IMM8 = IMM | SRC | L_8,
128 IMM8U = IMM | SRC | L_8U,
129 IMM16 = IMM | SRC | L_16,
130 IMM16U = IMM | SRC | L_16U,
131 IMM32 = IMM | SRC | L_32,
144 RS8 = SRC | L_8 | REG,
145 RS16 = SRC | L_16 | REG,
146 RS32 = SRC | L_32 | REG,
148 RSP = SRC | L_P | REG
[all...] |
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| tic54x.h | 49 OP_SRC1, /* src accumulator in bit 8 */
50 OP_SRC, /* src accumulator in bit 9 */
100 #define SRC(OP) ((OP)&0x200)
|
| h8300.h | 101 SRC = 0x10000,
127 IMM8 = IMM | SRC | L_8,
128 IMM8U = IMM | SRC | L_8U,
129 IMM16 = IMM | SRC | L_16,
130 IMM16U = IMM | SRC | L_16U,
131 IMM32 = IMM | SRC | L_32,
144 RS8 = SRC | L_8 | REG,
145 RS16 = SRC | L_16 | REG,
146 RS32 = SRC | L_32 | REG,
148 RSP = SRC | L_P | REG
[all...] |
| /src/external/gpl3/gdb/dist/include/opcode/ |
| tic54x.h | 49 OP_SRC1, /* src accumulator in bit 8 */
50 OP_SRC, /* src accumulator in bit 9 */
100 #define SRC(OP) ((OP)&0x200)
|
| h8300.h | 101 SRC = 0x10000,
127 IMM8 = IMM | SRC | L_8,
128 IMM8U = IMM | SRC | L_8U,
129 IMM16 = IMM | SRC | L_16,
130 IMM16U = IMM | SRC | L_16U,
131 IMM32 = IMM | SRC | L_32,
144 RS8 = SRC | L_8 | REG,
145 RS16 = SRC | L_16 | REG,
146 RS32 = SRC | L_32 | REG,
148 RSP = SRC | L_P | REG
[all...] |
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| tic54x.h | 49 OP_SRC1, /* src accumulator in bit 8 */
50 OP_SRC, /* src accumulator in bit 9 */
100 #define SRC(OP) ((OP)&0x200)
|
| /src/sys/dev/ic/ |
| summitreg.h | 206 #define IBO_SRC 4 /* src alpha */
207 #define IBO_ONE_MINUS_SRC 5 /* 1 - src alpha */
211 #define SRC(n) ((n) << 4)
|
| /src/external/gpl3/gdb/dist/sim/msp430/ |
| msp430-sim.c | 832 #define SRC get_op (sd, opcode, 1)
839 int s2 = SRC; \
1137 DEST (SRC);
1147 u2 = SRC;
1163 u2 = SRC;
1179 u2 = SRC;
1195 u2 = SRC;
1211 u2 = SRC;
1227 u2 = SRC;
1241 u2 = SRC;
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/msp430/ |
| msp430-sim.c | 832 #define SRC get_op (sd, opcode, 1)
839 int s2 = SRC; \
1137 DEST (SRC);
1147 u2 = SRC;
1163 u2 = SRC;
1179 u2 = SRC;
1195 u2 = SRC;
1211 u2 = SRC;
1227 u2 = SRC;
1241 u2 = SRC;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 617 Register Src = RI.getSubReg(SrcReg, SubIdx);
619 bool AlignedSrc = ((Src - AMDGPU::SGPR0) % 2) == 0;
1984 for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
1993 Register Src = SrcOp.getReg();
1994 if (Src.isPhysical())
1995 MovDPP.addReg(RI.getSubReg(Src, Sub));
1997 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
2774 // Any src operand can be used for the legality check.
3157 .addImm(0) // Src mods
4698 // DS instructions with 2 src operands also must have tied RC
[all...] |
