HomeSort by: relevance | last modified time | path
    Searched defs:SReg (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPreEmitPeephole.cpp 69 // sreg = -1 or 0
70 // vcc = S_AND_B64 exec, sreg or S_ANDN2_B64 exec, sreg
119 Register SReg;
121 SReg = Op2.getReg();
125 if (M->definesRegister(SReg, TRI))
127 if (M->modifiesRegister(SReg, TRI))
129 ReadsSreg |= M->readsRegister(SReg, TRI);
135 // First if sreg is only used in the AND instruction fold the immediate
168 if (SReg == ExecReg)
    [all...]
SIShrinkInstructions.cpp 761 Register SReg = Src2->getReg();
762 if (SReg.isVirtual()) {
763 MRI.setRegAllocationHint(SReg, 0, VCCReg);
766 if (SReg != VCCReg)
SIInstrInfo.cpp 1057 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1058 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
1065 .addReg(SReg);
1070 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1072 : AMDGPU::S_CSELECT_B64), SReg)
1080 .addReg(SReg);
1084 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
1086 : AMDGPU::S_CSELECT_B64), SReg)
1094 .addReg(SReg);
1100 Register SReg = MRI.createVirtualRegister(BoolXExecRC)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegisterScavenging.cpp 546 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
549 if (!isRegUsed(SReg)) {
550 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
551 return SReg;
557 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
561 << printReg(SReg, TRI) << "\n");
563 return SReg;
654 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
656 MRI.replaceRegWith(VReg, SReg);
658 return SReg;
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
i386-opc.h 880 SReg, /* Segment register */
  /src/external/gpl3/binutils.old/dist/opcodes/
i386-opc.h 867 SReg, /* Segment register */
  /src/external/gpl3/gdb/dist/opcodes/
i386-opc.h 834 SReg, /* Segment register */
  /src/external/gpl3/gdb.old/dist/opcodes/
i386-opc.h 817 SReg, /* Segment register */
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 4861 unsigned SReg = Inst.getOperand(1).getReg();
4869 if (DReg == SReg) {
4877 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4908 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4924 unsigned SReg = Inst.getOperand(1).getReg();
4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4941 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
4950 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 11316 Register SReg = RegInfo.createVirtualRegister(GPRC);
11317 BuildMI(BB, dl, TII->get(PPC::AND), SReg)
11320 unsigned ValueReg = SReg;
11325 .addReg(SReg)

Completed in 62 milliseconds