1 /* $NetBSD: sscom_reg.h,v 1.4 2021/09/13 23:31:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Fujitsu Component Limited 5 * Copyright (c) 2002, 2003 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 36 /* 37 * Register definitions for the Exynos[45] chipsets UARTs 38 */ 39 #ifndef _ARM_SAMSUNG_SSCOM_REG_H_ 40 #define _ARM_SAMSUNG_SSCOM_REG_H_ 41 42 43 #define SSCOM_ULCON 0x00 /* UART line control */ 44 #define ULCON_IR __BIT(6) 45 #define ULCON_PARITY __BITS(5,3) 46 #define ULCON_PARITY_NONE __SHIFTIN(0, ULCON_PARITY) 47 #define ULCON_PARITY_ODD __SHIFTIN(4, ULCON_PARITY) 48 #define ULCON_PARITY_EVEN __SHIFTIN(5, ULCON_PARITY) 49 #define ULCON_PARITY_ONE __SHIFTIN(6, ULCON_PARITY) 50 #define ULCON_PARITY_ZERO __SHIFTIN(7, ULCON_PARITY) 51 #define ULCON_STOP __BIT(2) 52 #define ULCON_LENGTH __BITS(1,0) 53 #define ULCON_LENGTH_5 0 54 #define ULCON_LENGTH_6 1 55 #define ULCON_LENGTH_7 2 56 #define ULCON_LENGTH_8 3 57 #define SSCOM_UCON 0x04 /* UART control */ 58 #define UCON_TXDMA_BRST __BITS(22,20) 59 #define UCON_TXDMA_BRST_1 __SHIFTIN(0, UCON_TXDMA) 60 #define UCON_TXDMA_BRST_4 __SHIFTIN(1, UCON_TXDMA) 61 #define UCON_TXDMA_BRST_8 __SHIFTIN(2, UCON_TXDMA) 62 #define UCON_TXDMA_BRST_16 __SHIFTIN(3, UCON_TXDMA) 63 #define UCON_RXDMA_BRST __BITS(18,16) 64 #define UCON_RXDMA_BRST_1 __SHIFTIN(0, UCON_RXDMA) 65 #define UCON_RXDMA_BRST_4 __SHIFTIN(1, UCON_RXDMA) 66 #define UCON_RXDMA_BRST_8 __SHIFTIN(2, UCON_RXDMA) 67 #define UCON_RXDMA_BRST_16 __SHIFTIN(3, UCON_RXDMA) 68 #define UCON_RXTO __BITS(15,12) 69 #define UCON_S5L_TXTHRESH __BIT(13) /* Apple specific */ 70 #define UCON_S5L_RXTHRESH __BIT(12) /* Apple specific */ 71 #define UCON_RXTO_FIFO_EMPTY __BIT(11) 72 #define UCON_RXTO_DMA_FSM_STOP __BIT(10) 73 #define UCON_TXINT_TYPE __BIT(9) /* Tx interrupt. 0=pulse,1=level */ 74 #define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE /* 4412 mandatory */ 75 #define UCON_TXINT_TYPE_PULSE 0 76 #define UCON_S5L_RX_TIMEOUT __BIT(9) /* Apple specific */ 77 #define UCON_RXINT_TYPE __BIT(8) /* Rx interrupt */ 78 #define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE /* 4412 mandatory */ 79 #define UCON_RXINT_TYPE_PULSE __SHIFTIN(0,UCON_RXINT_TYPE) 80 #define UCON_TOINT __BIT(7) /* Rx timeout interrupt */ 81 #define UCON_ERRINT __BIT(6) /* receive error interrupt */ 82 #define UCON_LOOP __BIT(5) /* loopback */ 83 #define UCON_SBREAK __BIT(4) /* send break */ 84 #define UCON_TXMODE __BITS(3,2) 85 #define UCON_TXMODE_DISABLE __SHIFTIN(0, UCON_TXMODE) 86 #define UCON_TXMODE_INT __SHIFTIN(1, UCON_TXMODE) 87 #define UCON_TXMODE_DMA __SHIFTIN(2, UCON_TXMODE) 88 #define UCON_TXMODE_MASK __SHIFTIN(3, UCON_TXMODE) 89 #define UCON_RXMODE __BITS(1,0) 90 #define UCON_RXMODE_DISABLE __SHIFTIN(1, UCON_RXMODE) 91 #define UCON_RXMODE_INT __SHIFTIN(1, UCON_RXMODE) 92 #define UCON_RXMODE_DMA __SHIFTIN(2, UCON_RXMODE) 93 #define UCON_RXMODE_MASK __SHIFTIN(3, UCON_RXMODE) 94 #define SSCOM_UFCON 0x08 /* FIFO control */ 95 #define UFCON_TXTRIGGER __BITS(10,8) 96 #define UFCON_RXTRIGGER __BITS(6,4) 97 #define UFCON_TXFIFO_RESET __BIT(2) 98 #define UFCON_RXFIFO_RESET __BIT(1) 99 #define UFCON_FIFO_ENABLE __BIT(0) 100 #define SSCOM_UMCON 0x0c /* MODEM control */ 101 #define UMCON_RTSTRIGGER __BITS(7,5) 102 #define UMCON_AFC __BIT(4) 103 #define UMCON_MODEMINT_ENABLE __BIT(3) 104 #define UMCON_RTS __BIT(0) /* Request to send */ 105 #define SSCOM_UTRSTAT 0x10 /* Status register */ 106 #define UTRSTAT_RXFIFOCNT __BITS(23,16) 107 #define UTRSTAT_TXDMA_FSM __BITS(15,12) 108 #define UTRSTAT_RXDMA_FSM __BITS(11,8) 109 #define UTRSTAT_S5L_RX_TIMEOUT __BIT(9) /* Apple specific */ 110 #define UTRSTAT_S5L_TXTHRESH __BIT(5) /* Apple specific */ 111 #define UTRSTAT_S5L_RXTHRESH __BIT(4) /* Apple specific */ 112 #define UTRSTAT_RXTIMEOUT __BIT(3) 113 #define UTRSTAT_TXSHIFTER_EMPTY __BIT(2) 114 #define UTRSTAT_TXEMPTY __BIT(1) /* TX fifo or buffer empty */ 115 #define UTRSTAT_RXREADY __BIT(0) /* RX fifo or buffer is not empty */ 116 #define SSCOM_UERSTAT 0x14 /* Error status register */ 117 #define UERSTAT_BREAK __BIT(3) /* Break signal */ 118 #define UERSTAT_FRAME __BIT(2) /* Frame error */ 119 #define UERSTAT_PARITY __BIT(1) /* Parity error */ 120 #define UERSTAT_OVERRUN __BIT(0) /* Overrun */ 121 #define UERSTAT_ALL_ERRORS (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY) 122 #define SSCOM_UFSTAT 0x18 /* Fifo status register */ 123 #define UFSTAT_TXFULL __BIT(24) /* Tx fifo full */ 124 #define UFSTAT_TXCOUNT __BITS(23,16) /* TX FIFO count */ 125 #define UFSTAT_RXERROR __BIT(9) 126 #define UFSTAT_S5L_TXFULL __BIT(9) /* Tx fifo full (Apple) */ 127 #define UFSTAT_RXFULL __BIT(8) /* Rx fifo full */ 128 #define UFSTAT_S5L_RXFULL __BIT(8) /* Rx fifo full (Apple) */ 129 #define UFSTAT_RXCOUNT __BITS(7,0) /* RX FIFO count */ 130 #define UFSTAT_S5L_RXCOUNT __BITS(3,0) /* RX FIFO count (Apple) */ 131 #define SSCOM_UMSTAT 0x1c /* Modem status register */ 132 #define UMSTAT_DCTS __BIT(4) 133 #define UMSTAT_CTS __BIT(0) /* Clear to send */ 134 #if _BYTE_ORDER == _LITTLE_ENDIAN 135 #define SSCOM_UTXH 0x20 /* Transmit data register */ 136 #define SSCOM_URXH 0x24 /* Receive data register */ 137 #else 138 #define SSCOM_UTXH 0x23 /* Transmit data register */ 139 #define SSCOM_URXH 0x27 /* Receive data register */ 140 #endif 141 #define SSCOM_UBRDIV 0x28 /* baud-rate divisor [15:0] */ 142 #define SSCOM_UFRACVAL 0x2C /* baud-rate fraction [3:0] */ 143 144 /* Interrupt controller */ 145 #define SSCOM_UINTP 0x30 /* interrupt source */ 146 #define SSCOM_UINTSP 0x34 /* pending interrupts */ 147 #define SSCOM_UINTM 0x38 /* interrupt masking */ 148 #define UINT_MODEM __BIT(3) 149 #define UINT_TXD __BIT(2) 150 #define UINT_ERROR __BIT(1) 151 #define UINT_RXD __BIT(0) 152 153 #define SSCOM_SIZE 0x3C 154 155 #endif /* _ARM_SAMSUNG_SSCOM_REG_H_ */ 156 157
Indexes created Wed Sep 24 22:09:59 GMT 2025