1 /* $NetBSD: if_stge.c,v 1.94 2025/10/04 04:44:21 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the Sundance Tech. TC9021 10/100/1000 34 * Ethernet controller. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.94 2025/10/04 04:44:21 thorpej Exp $"); 39 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 #include <sys/queue.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #include <sys/bus.h> 60 #include <sys/intr.h> 61 62 #include <dev/mii/mii.h> 63 #include <dev/mii/miivar.h> 64 #include <dev/mii/mii_bitbang.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcidevs.h> 69 70 #include <dev/pci/if_stgereg.h> 71 72 #include <prop/proplib.h> 73 74 /* #define STGE_CU_BUG 1 */ 75 #define STGE_VLAN_UNTAG 1 76 /* #define STGE_VLAN_CFI 1 */ 77 78 /* 79 * Transmit descriptor list size. 80 */ 81 #define STGE_NTXDESC 256 82 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 83 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 84 85 /* 86 * Receive descriptor list size. 87 */ 88 #define STGE_NRXDESC 256 89 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 90 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 91 92 /* 93 * Only interrupt every N frames. Must be a power-of-two. 94 */ 95 #define STGE_TXINTR_SPACING 16 96 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 97 98 /* 99 * Control structures are DMA'd to the TC9021 chip. We allocate them in 100 * a single clump that maps to a single DMA segment to make several things 101 * easier. 102 */ 103 struct stge_control_data { 104 /* 105 * The transmit descriptors. 106 */ 107 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 108 109 /* 110 * The receive descriptors. 111 */ 112 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 113 }; 114 115 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 116 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 117 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 118 119 /* 120 * Software state for transmit and receive jobs. 121 */ 122 struct stge_descsoft { 123 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 124 bus_dmamap_t ds_dmamap; /* our DMA map */ 125 }; 126 127 /* 128 * Software state per device. 129 */ 130 struct stge_softc { 131 device_t sc_dev; /* generic device information */ 132 bus_space_tag_t sc_st; /* bus space tag */ 133 bus_space_handle_t sc_sh; /* bus space handle */ 134 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 135 struct ethercom sc_ethercom; /* ethernet common data */ 136 int sc_rev; /* silicon revision */ 137 138 void *sc_ih; /* interrupt cookie */ 139 140 struct mii_data sc_mii; /* MII/media information */ 141 142 callout_t sc_tick_ch; /* tick callout */ 143 144 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 145 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 146 147 /* 148 * Software state for transmit and receive descriptors. 149 */ 150 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 151 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 152 153 /* 154 * Control data structures. 155 */ 156 struct stge_control_data *sc_control_data; 157 #define sc_txdescs sc_control_data->scd_txdescs 158 #define sc_rxdescs sc_control_data->scd_rxdescs 159 160 #ifdef STGE_EVENT_COUNTERS 161 /* 162 * Event counters. 163 */ 164 struct evcnt sc_ev_txstall; /* Tx stalled */ 165 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */ 166 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */ 167 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 168 169 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 170 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 171 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 172 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 173 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 174 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 175 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */ 176 177 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 178 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 179 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */ 180 181 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 182 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 183 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 184 #endif /* STGE_EVENT_COUNTERS */ 185 186 int sc_txpending; /* number of Tx requests pending */ 187 int sc_txdirty; /* first dirty Tx descriptor */ 188 int sc_txlast; /* last used Tx descriptor */ 189 190 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 191 int sc_rxdiscard; 192 int sc_rxlen; 193 struct mbuf *sc_rxhead; 194 struct mbuf *sc_rxtail; 195 struct mbuf **sc_rxtailp; 196 197 int sc_txthresh; /* Tx threshold */ 198 uint32_t sc_usefiber:1; /* if we're fiber */ 199 uint32_t sc_stge1023:1; /* are we a 1023 */ 200 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 201 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 202 uint16_t sc_IntEnable; /* prototype IntEnable register */ 203 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 204 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 205 }; 206 207 #define STGE_RXCHAIN_RESET(sc) \ 208 do { \ 209 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 210 *(sc)->sc_rxtailp = NULL; \ 211 (sc)->sc_rxlen = 0; \ 212 } while (/*CONSTCOND*/0) 213 214 #define STGE_RXCHAIN_LINK(sc, m) \ 215 do { \ 216 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 217 (sc)->sc_rxtailp = &(m)->m_next; \ 218 } while (/*CONSTCOND*/0) 219 220 /* 221 * Register access macros 222 */ 223 #define CSR_WRITE_4(_sc, reg, val) \ 224 bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 225 #define CSR_WRITE_2(_sc, reg, val) \ 226 bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 227 #define CSR_WRITE_1(_sc, reg, val) \ 228 bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 229 230 #define CSR_READ_4(_sc, reg) \ 231 bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg)) 232 #define CSR_READ_2(_sc, reg) \ 233 bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg)) 234 #define CSR_READ_1(_sc, reg) \ 235 bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg)) 236 237 #define STGE_TIMEOUT 1000 238 239 #ifdef STGE_EVENT_COUNTERS 240 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++ 241 #else 242 #define STGE_EVCNT_INCR(ev) /* nothing */ 243 #endif 244 245 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 246 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 247 248 #define STGE_CDTXSYNC(sc, x, ops) \ 249 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 250 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 251 252 #define STGE_CDRXSYNC(sc, x, ops) \ 253 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 254 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 255 256 #define STGE_INIT_RXDESC(sc, x) \ 257 do { \ 258 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 259 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 260 \ 261 /* \ 262 * Note: We scoot the packet forward 2 bytes in the buffer \ 263 * so that the payload after the Ethernet header is aligned \ 264 * to a 4-byte boundary. \ 265 */ \ 266 __rfd->rfd_frag.frag_word0 = \ 267 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 268 FRAG_LEN(MCLBYTES - 2)); \ 269 __rfd->rfd_next = \ 270 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 271 __rfd->rfd_status = 0; \ 272 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 273 } while (/*CONSTCOND*/0) 274 275 static void stge_start(struct ifnet *); 276 static void stge_watchdog(struct ifnet *); 277 static int stge_ioctl(struct ifnet *, u_long, void *); 278 static int stge_init(struct ifnet *); 279 static void stge_stop(struct ifnet *, int); 280 281 static bool stge_shutdown(device_t, int); 282 283 static void stge_reset(struct stge_softc *); 284 static void stge_rxdrain(struct stge_softc *); 285 static int stge_add_rxbuf(struct stge_softc *, int); 286 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *); 287 static void stge_tick(void *); 288 289 static void stge_stats_update(struct stge_softc *); 290 291 static void stge_set_filter(struct stge_softc *); 292 293 static int stge_intr(void *); 294 static void stge_txintr(struct stge_softc *); 295 static void stge_rxintr(struct stge_softc *); 296 297 static int stge_mii_readreg(device_t, int, int, uint16_t *); 298 static int stge_mii_writereg(device_t, int, int, uint16_t); 299 static void stge_mii_statchg(struct ifnet *); 300 301 static int stge_match(device_t, cfdata_t, void *); 302 static void stge_attach(device_t, device_t, void *); 303 304 int stge_copy_small = 0; 305 306 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc), 307 stge_match, stge_attach, NULL, NULL); 308 309 static uint32_t stge_mii_bitbang_read(device_t); 310 static void stge_mii_bitbang_write(device_t, uint32_t); 311 312 static const struct mii_bitbang_ops stge_mii_bitbang_ops = { 313 stge_mii_bitbang_read, 314 stge_mii_bitbang_write, 315 { 316 PC_MgmtData, /* MII_BIT_MDO */ 317 PC_MgmtData, /* MII_BIT_MDI */ 318 PC_MgmtClk, /* MII_BIT_MDC */ 319 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */ 320 0, /* MII_BIT_DIR_PHY_HOST */ 321 } 322 }; 323 324 /* 325 * Devices supported by this driver. 326 */ 327 static const struct stge_product { 328 pci_vendor_id_t stge_vendor; 329 pci_product_id_t stge_product; 330 const char *stge_name; 331 } stge_products[] = { 332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023, 333 "Sundance ST-1023 Gigabit Ethernet" }, 334 335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021, 336 "Sundance ST-2021 Gigabit Ethernet" }, 337 338 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021, 339 "Tamarack TC9021 Gigabit Ethernet" }, 340 341 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT, 342 "Tamarack TC9021 Gigabit Ethernet" }, 343 344 /* 345 * The Sundance sample boards use the Sundance vendor ID, 346 * but the Tamarack product ID. 347 */ 348 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021, 349 "Sundance TC9021 Gigabit Ethernet" }, 350 351 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT, 352 "Sundance TC9021 Gigabit Ethernet" }, 353 354 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000, 355 "D-Link DL-4000 Gigabit Ethernet" }, 356 357 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021, 358 "Antares Gigabit Ethernet" }, 359 360 { 0, 0, 361 NULL }, 362 }; 363 364 static const struct stge_product * 365 stge_lookup(const struct pci_attach_args *pa) 366 { 367 const struct stge_product *sp; 368 369 for (sp = stge_products; sp->stge_name != NULL; sp++) { 370 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor && 371 PCI_PRODUCT(pa->pa_id) == sp->stge_product) 372 return (sp); 373 } 374 return (NULL); 375 } 376 377 static int 378 stge_match(device_t parent, cfdata_t cf, void *aux) 379 { 380 struct pci_attach_args *pa = aux; 381 382 if (stge_lookup(pa) != NULL) 383 return (1); 384 385 return (0); 386 } 387 388 static void 389 stge_attach(device_t parent, device_t self, void *aux) 390 { 391 struct stge_softc *sc = device_private(self); 392 struct pci_attach_args *pa = aux; 393 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 394 struct mii_data * const mii = &sc->sc_mii; 395 pci_chipset_tag_t pc = pa->pa_pc; 396 pci_intr_handle_t ih; 397 const char *intrstr = NULL; 398 bus_space_tag_t iot, memt; 399 bus_space_handle_t ioh, memh; 400 bus_dma_segment_t seg; 401 int ioh_valid, memh_valid; 402 int i, rseg, error; 403 const struct stge_product *sp; 404 uint8_t enaddr[ETHER_ADDR_LEN]; 405 char intrbuf[PCI_INTRSTR_LEN]; 406 407 sc->sc_dev = self; 408 callout_init(&sc->sc_tick_ch, 0); 409 callout_setfunc(&sc->sc_tick_ch, stge_tick, sc); 410 411 sp = stge_lookup(pa); 412 if (sp == NULL) { 413 printf("\n"); 414 panic("ste_attach: impossible"); 415 } 416 417 sc->sc_rev = PCI_REVISION(pa->pa_class); 418 419 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1); 420 421 /* 422 * Map the device. 423 */ 424 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA, 425 PCI_MAPREG_TYPE_IO, 0, 426 &iot, &ioh, NULL, NULL) == 0); 427 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA, 428 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 429 &memt, &memh, NULL, NULL) == 0); 430 431 if (memh_valid) { 432 sc->sc_st = memt; 433 sc->sc_sh = memh; 434 } else if (ioh_valid) { 435 sc->sc_st = iot; 436 sc->sc_sh = ioh; 437 } else { 438 aprint_error_dev(self, "unable to map device registers\n"); 439 return; 440 } 441 442 /* 443 * We have a 40-bit limit on our DMA addresses. This isn't an 444 * issue if we're only using a 32-bit DMA tag, but we have to 445 * account for it if the 64-bit DMA tag is available. 446 */ 447 if (pci_dma64_available(pa)) { 448 if (bus_dmatag_subregion(pa->pa_dmat64, 449 0, 450 (bus_addr_t)FRAG_ADDR_MASK, 451 &sc->sc_dmat, 452 BUS_DMA_WAITOK) != 0) { 453 aprint_error_dev(self, 454 "WARNING: failed to restrict dma range," 455 " falling back to parent bus dma range\n"); 456 sc->sc_dmat = pa->pa_dmat64; 457 } 458 } else { 459 sc->sc_dmat = pa->pa_dmat; 460 } 461 462 /* Enable bus mastering. */ 463 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 464 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 465 PCI_COMMAND_MASTER_ENABLE); 466 467 /* power up chip */ 468 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 469 error != EOPNOTSUPP) { 470 aprint_error_dev(self, "cannot activate %d\n", error); 471 return; 472 } 473 /* 474 * Map and establish our interrupt. 475 */ 476 if (pci_intr_map(pa, &ih)) { 477 aprint_error_dev(self, "unable to map interrupt\n"); 478 return; 479 } 480 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 481 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, stge_intr, sc, 482 device_xname(self)); 483 if (sc->sc_ih == NULL) { 484 aprint_error_dev(self, "unable to establish interrupt"); 485 if (intrstr != NULL) 486 aprint_error(" at %s", intrstr); 487 aprint_error("\n"); 488 return; 489 } 490 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 491 492 /* 493 * Allocate the control data structures, and create and load the 494 * DMA map for it. 495 */ 496 if ((error = bus_dmamem_alloc(sc->sc_dmat, 497 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 498 0)) != 0) { 499 aprint_error_dev(self, 500 "unable to allocate control data, error = %d\n", error); 501 goto fail_0; 502 } 503 504 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 505 sizeof(struct stge_control_data), (void **)&sc->sc_control_data, 506 BUS_DMA_COHERENT)) != 0) { 507 aprint_error_dev(self, 508 "unable to map control data, error = %d\n", error); 509 goto fail_1; 510 } 511 512 if ((error = bus_dmamap_create(sc->sc_dmat, 513 sizeof(struct stge_control_data), 1, 514 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 515 aprint_error_dev(self, 516 "unable to create control data DMA map, error = %d\n", 517 error); 518 goto fail_2; 519 } 520 521 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 522 sc->sc_control_data, sizeof(struct stge_control_data), NULL, 523 0)) != 0) { 524 aprint_error_dev(self, 525 "unable to load control data DMA map, error = %d\n", 526 error); 527 goto fail_3; 528 } 529 530 /* 531 * Create the transmit buffer DMA maps. Note that rev B.3 532 * and earlier seem to have a bug regarding multi-fragment 533 * packets. We need to limit the number of Tx segments on 534 * such chips to 1. 535 */ 536 for (i = 0; i < STGE_NTXDESC; i++) { 537 if ((error = bus_dmamap_create(sc->sc_dmat, 538 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0, 539 &sc->sc_txsoft[i].ds_dmamap)) != 0) { 540 aprint_error_dev(self, 541 "unable to create tx DMA map %d, error = %d\n", 542 i, error); 543 goto fail_4; 544 } 545 } 546 547 /* 548 * Create the receive buffer DMA maps. 549 */ 550 for (i = 0; i < STGE_NRXDESC; i++) { 551 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 552 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) { 553 aprint_error_dev(self, 554 "unable to create rx DMA map %d, error = %d\n", 555 i, error); 556 goto fail_5; 557 } 558 sc->sc_rxsoft[i].ds_mbuf = NULL; 559 } 560 561 /* 562 * Determine if we're copper or fiber. It affects how we 563 * reset the card. 564 */ 565 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) 566 sc->sc_usefiber = 1; 567 else 568 sc->sc_usefiber = 0; 569 570 /* 571 * Reset the chip to a known state. 572 */ 573 stge_reset(sc); 574 575 /* 576 * Reading the station address from the EEPROM doesn't seem 577 * to work, at least on my sample boards. Instead, since 578 * the reset sequence does AutoInit, read it from the station 579 * address registers. For Sundance 1023 you can only read it 580 * from EEPROM. 581 */ 582 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) { 583 enaddr[0] = CSR_READ_2(sc, STGE_StationAddress0) & 0xff; 584 enaddr[1] = CSR_READ_2(sc, STGE_StationAddress0) >> 8; 585 enaddr[2] = CSR_READ_2(sc, STGE_StationAddress1) & 0xff; 586 enaddr[3] = CSR_READ_2(sc, STGE_StationAddress1) >> 8; 587 enaddr[4] = CSR_READ_2(sc, STGE_StationAddress2) & 0xff; 588 enaddr[5] = CSR_READ_2(sc, STGE_StationAddress2) >> 8; 589 sc->sc_stge1023 = 0; 590 } else { 591 if (! ether_getaddr(self, enaddr)) { 592 uint16_t myaddr[ETHER_ADDR_LEN / 2]; 593 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) { 594 stge_read_eeprom(sc, 595 STGE_EEPROM_StationAddress0 + i, 596 &myaddr[i]); 597 myaddr[i] = le16toh(myaddr[i]); 598 } 599 (void)memcpy(enaddr, myaddr, sizeof(enaddr)); 600 } 601 sc->sc_stge1023 = 1; 602 } 603 604 /* Set need_loaddspcode before mii_attach() */ 605 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e) { 606 device_setprop_bool(self, "need_loaddspcode", true); 607 } 608 609 aprint_normal_dev(self, "Ethernet address %s\n", 610 ether_sprintf(enaddr)); 611 612 /* 613 * Read some important bits from the PhyCtrl register. 614 */ 615 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) & 616 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 617 618 /* 619 * Initialize our media structures and probe the MII. 620 */ 621 mii->mii_ifp = ifp; 622 mii->mii_readreg = stge_mii_readreg; 623 mii->mii_writereg = stge_mii_writereg; 624 mii->mii_statchg = stge_mii_statchg; 625 sc->sc_ethercom.ec_mii = mii; 626 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 627 ether_mediastatus); 628 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 629 MII_OFFSET_ANY, MIIF_DOPAUSE); 630 if (LIST_FIRST(&mii->mii_phys) == NULL) { 631 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 632 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 633 } else 634 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 635 636 ifp = &sc->sc_ethercom.ec_if; 637 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 638 ifp->if_softc = sc; 639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 640 ifp->if_ioctl = stge_ioctl; 641 ifp->if_start = stge_start; 642 ifp->if_watchdog = stge_watchdog; 643 ifp->if_init = stge_init; 644 ifp->if_stop = stge_stop; 645 IFQ_SET_READY(&ifp->if_snd); 646 647 /* 648 * The manual recommends disabling early transmit, so we 649 * do. It's disabled anyway, if using IP checksumming, 650 * since the entire packet must be in the FIFO in order 651 * for the chip to perform the checksum. 652 */ 653 sc->sc_txthresh = 0x0fff; 654 655 /* 656 * Disable MWI if the PCI layer tells us to. 657 */ 658 sc->sc_DMACtrl = 0; 659 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0) 660 sc->sc_DMACtrl |= DMAC_MWIDisable; 661 662 /* 663 * We can support 802.1Q VLAN-sized frames and jumbo 664 * Ethernet frames. 665 * 666 * XXX Figure out how to do hw-assisted VLAN tagging in 667 * XXX a reasonable way on this chip. 668 */ 669 sc->sc_ethercom.ec_capabilities |= 670 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */ 671 ETHERCAP_VLAN_HWTAGGING; 672 sc->sc_ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 673 674 /* 675 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 676 */ 677 sc->sc_ethercom.ec_if.if_capabilities |= 678 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 679 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 680 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 681 682 /* 683 * Attach the interface. 684 */ 685 if_attach(ifp); 686 if_deferred_start_init(ifp, NULL); 687 ether_ifattach(ifp, enaddr); 688 689 #ifdef STGE_EVENT_COUNTERS 690 /* 691 * Attach event counters. 692 */ 693 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 694 NULL, device_xname(self), "txstall"); 695 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR, 696 NULL, device_xname(self), "txdmaintr"); 697 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR, 698 NULL, device_xname(self), "txindintr"); 699 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 700 NULL, device_xname(self), "rxintr"); 701 702 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 703 NULL, device_xname(self), "txseg1"); 704 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 705 NULL, device_xname(self), "txseg2"); 706 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 707 NULL, device_xname(self), "txseg3"); 708 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 709 NULL, device_xname(self), "txseg4"); 710 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 711 NULL, device_xname(self), "txseg5"); 712 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 713 NULL, device_xname(self), "txsegmore"); 714 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 715 NULL, device_xname(self), "txcopy"); 716 717 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 718 NULL, device_xname(self), "rxipsum"); 719 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 720 NULL, device_xname(self), "rxtcpsum"); 721 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 722 NULL, device_xname(self), "rxudpsum"); 723 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 724 NULL, device_xname(self), "txipsum"); 725 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 726 NULL, device_xname(self), "txtcpsum"); 727 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 728 NULL, device_xname(self), "txudpsum"); 729 #endif /* STGE_EVENT_COUNTERS */ 730 731 /* 732 * Make sure the interface is shutdown during reboot. 733 */ 734 if (pmf_device_register1(self, NULL, NULL, stge_shutdown)) 735 pmf_class_network_register(self, ifp); 736 else 737 aprint_error_dev(self, "couldn't establish power handler\n"); 738 739 return; 740 741 /* 742 * Free any resources we've allocated during the failed attach 743 * attempt. Do this in reverse order and fall through. 744 */ 745 fail_5: 746 for (i = 0; i < STGE_NRXDESC; i++) { 747 if (sc->sc_rxsoft[i].ds_dmamap != NULL) 748 bus_dmamap_destroy(sc->sc_dmat, 749 sc->sc_rxsoft[i].ds_dmamap); 750 } 751 fail_4: 752 for (i = 0; i < STGE_NTXDESC; i++) { 753 if (sc->sc_txsoft[i].ds_dmamap != NULL) 754 bus_dmamap_destroy(sc->sc_dmat, 755 sc->sc_txsoft[i].ds_dmamap); 756 } 757 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 758 fail_3: 759 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 760 fail_2: 761 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 762 sizeof(struct stge_control_data)); 763 fail_1: 764 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 765 fail_0: 766 return; 767 } 768 769 /* 770 * stge_shutdown: 771 * 772 * Make sure the interface is stopped at reboot time. 773 */ 774 static bool 775 stge_shutdown(device_t self, int howto) 776 { 777 struct stge_softc *sc = device_private(self); 778 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 779 780 stge_stop(ifp, 1); 781 stge_reset(sc); 782 return true; 783 } 784 785 static void 786 stge_dma_wait(struct stge_softc *sc) 787 { 788 int i; 789 790 for (i = 0; i < STGE_TIMEOUT; i++) { 791 delay(2); 792 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) 793 break; 794 } 795 796 if (i == STGE_TIMEOUT) 797 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev)); 798 } 799 800 /* 801 * stge_start: [ifnet interface function] 802 * 803 * Start packet transmission on the interface. 804 */ 805 static void 806 stge_start(struct ifnet *ifp) 807 { 808 struct stge_softc *sc = ifp->if_softc; 809 struct mbuf *m0; 810 struct stge_descsoft *ds; 811 struct stge_tfd *tfd; 812 bus_dmamap_t dmamap; 813 int error, firsttx, nexttx, opending, seg, totlen; 814 uint64_t csum_flags; 815 816 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 817 return; 818 819 /* 820 * Remember the previous number of pending transmissions 821 * and the first descriptor we will use. 822 */ 823 opending = sc->sc_txpending; 824 firsttx = STGE_NEXTTX(sc->sc_txlast); 825 826 /* 827 * Loop through the send queue, setting up transmit descriptors 828 * until we drain the queue, or use up all available transmit 829 * descriptors. 830 */ 831 for (;;) { 832 uint64_t tfc; 833 bool have_vtag; 834 uint16_t vtag; 835 836 /* 837 * Grab a packet off the queue. 838 */ 839 IFQ_POLL(&ifp->if_snd, m0); 840 if (m0 == NULL) 841 break; 842 843 /* 844 * Leave one unused descriptor at the end of the 845 * list to prevent wrapping completely around. 846 */ 847 if (sc->sc_txpending == (STGE_NTXDESC - 1)) { 848 STGE_EVCNT_INCR(&sc->sc_ev_txstall); 849 break; 850 } 851 852 /* 853 * See if we have any VLAN stuff. 854 */ 855 have_vtag = vlan_has_tag(m0); 856 if (have_vtag) 857 vtag = vlan_get_tag(m0); 858 859 /* 860 * Get the last and next available transmit descriptor. 861 */ 862 nexttx = STGE_NEXTTX(sc->sc_txlast); 863 tfd = &sc->sc_txdescs[nexttx]; 864 ds = &sc->sc_txsoft[nexttx]; 865 866 dmamap = ds->ds_dmamap; 867 868 /* 869 * Load the DMA map. If this fails, the packet either 870 * didn't fit in the allotted number of segments, or we 871 * were short on resources. For the too-many-segments 872 * case, we simply report an error and drop the packet, 873 * since we can't sanely copy a jumbo packet to a single 874 * buffer. 875 */ 876 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 877 BUS_DMA_NOWAIT); 878 if (error) { 879 if (error == EFBIG) { 880 printf("%s: Tx packet consumes too many " 881 "DMA segments, dropping...\n", 882 device_xname(sc->sc_dev)); 883 IFQ_DEQUEUE(&ifp->if_snd, m0); 884 m_freem(m0); 885 continue; 886 } 887 /* 888 * Short on resources, just stop for now. 889 */ 890 break; 891 } 892 893 IFQ_DEQUEUE(&ifp->if_snd, m0); 894 895 /* 896 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 897 */ 898 899 /* Sync the DMA map. */ 900 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 901 BUS_DMASYNC_PREWRITE); 902 903 /* Initialize the fragment list. */ 904 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) { 905 tfd->tfd_frags[seg].frag_word0 = 906 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) | 907 FRAG_LEN(dmamap->dm_segs[seg].ds_len)); 908 totlen += dmamap->dm_segs[seg].ds_len; 909 } 910 911 #ifdef STGE_EVENT_COUNTERS 912 switch (dmamap->dm_nsegs) { 913 case 1: 914 STGE_EVCNT_INCR(&sc->sc_ev_txseg1); 915 break; 916 case 2: 917 STGE_EVCNT_INCR(&sc->sc_ev_txseg2); 918 break; 919 case 3: 920 STGE_EVCNT_INCR(&sc->sc_ev_txseg3); 921 break; 922 case 4: 923 STGE_EVCNT_INCR(&sc->sc_ev_txseg4); 924 break; 925 case 5: 926 STGE_EVCNT_INCR(&sc->sc_ev_txseg5); 927 break; 928 default: 929 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore); 930 break; 931 } 932 #endif /* STGE_EVENT_COUNTERS */ 933 934 /* 935 * Initialize checksumming flags in the descriptor. 936 * Byte-swap constants so the compiler can optimize. 937 */ 938 csum_flags = 0; 939 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 940 STGE_EVCNT_INCR(&sc->sc_ev_txipsum); 941 csum_flags |= TFD_IPChecksumEnable; 942 } 943 944 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 945 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum); 946 csum_flags |= TFD_TCPChecksumEnable; 947 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 948 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum); 949 csum_flags |= TFD_UDPChecksumEnable; 950 } 951 952 /* 953 * Initialize the descriptor and give it to the chip. 954 * Check to see if we have a VLAN tag to insert. 955 */ 956 957 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) | 958 TFD_FragCount(seg) | csum_flags | 959 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ? 960 TFD_TxDMAIndicate : 0); 961 if (have_vtag) { 962 #if 0 963 struct ether_header *eh = 964 mtod(m0, struct ether_header *); 965 uint16_t etype = ntohs(eh->ether_type); 966 printf("%s: xmit (tag %d) etype %x\n", 967 ifp->if_xname, *mtod(n, int *), etype); 968 #endif 969 tfc |= TFD_VLANTagInsert | 970 #ifdef STGE_VLAN_CFI 971 TFD_CFI | 972 #endif 973 TFD_VID(vtag); 974 } 975 tfd->tfd_control = htole64(tfc); 976 977 /* Sync the descriptor. */ 978 STGE_CDTXSYNC(sc, nexttx, 979 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 980 981 /* 982 * Kick the transmit DMA logic. 983 */ 984 CSR_WRITE_4(sc, STGE_DMACtrl, 985 sc->sc_DMACtrl | DMAC_TxDMAPollNow); 986 987 /* 988 * Store a pointer to the packet so we can free it later. 989 */ 990 ds->ds_mbuf = m0; 991 992 /* Advance the tx pointer. */ 993 sc->sc_txpending++; 994 sc->sc_txlast = nexttx; 995 996 /* 997 * Pass the packet to any BPF listeners. 998 */ 999 bpf_mtap(ifp, m0, BPF_D_OUT); 1000 } 1001 1002 if (sc->sc_txpending != opending) { 1003 /* 1004 * We enqueued packets. If the transmitter was idle, 1005 * reset the txdirty pointer. 1006 */ 1007 if (opending == 0) 1008 sc->sc_txdirty = firsttx; 1009 1010 /* Set a watchdog timer in case the chip flakes out. */ 1011 ifp->if_timer = 5; 1012 } 1013 } 1014 1015 /* 1016 * stge_watchdog: [ifnet interface function] 1017 * 1018 * Watchdog timer handler. 1019 */ 1020 static void 1021 stge_watchdog(struct ifnet *ifp) 1022 { 1023 struct stge_softc *sc = ifp->if_softc; 1024 1025 /* 1026 * Sweep up first, since we don't interrupt every frame. 1027 */ 1028 stge_txintr(sc); 1029 if (sc->sc_txpending != 0) { 1030 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1031 if_statinc(ifp, if_oerrors); 1032 1033 (void) stge_init(ifp); 1034 1035 /* Try to get more packets going. */ 1036 stge_start(ifp); 1037 } 1038 } 1039 1040 /* 1041 * stge_ioctl: [ifnet interface function] 1042 * 1043 * Handle control requests from the operator. 1044 */ 1045 static int 1046 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1047 { 1048 struct stge_softc *sc = ifp->if_softc; 1049 int s, error; 1050 1051 s = splnet(); 1052 1053 error = ether_ioctl(ifp, cmd, data); 1054 if (error == ENETRESET) { 1055 error = 0; 1056 1057 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1058 ; 1059 else if (ifp->if_flags & IFF_RUNNING) { 1060 /* 1061 * Multicast list has changed; set the hardware filter 1062 * accordingly. 1063 */ 1064 stge_set_filter(sc); 1065 } 1066 } 1067 1068 /* Try to get more packets going. */ 1069 stge_start(ifp); 1070 1071 splx(s); 1072 return (error); 1073 } 1074 1075 /* 1076 * stge_intr: 1077 * 1078 * Interrupt service routine. 1079 */ 1080 static int 1081 stge_intr(void *arg) 1082 { 1083 struct stge_softc *sc = arg; 1084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1085 uint32_t txstat; 1086 int wantinit; 1087 uint16_t isr; 1088 1089 if ((CSR_READ_2(sc, STGE_IntStatus) & IS_InterruptStatus) == 0) 1090 return (0); 1091 1092 for (wantinit = 0; wantinit == 0;) { 1093 isr = CSR_READ_2(sc, STGE_IntStatusAck); 1094 if ((isr & sc->sc_IntEnable) == 0) 1095 break; 1096 1097 /* Host interface errors. */ 1098 if (isr & IS_HostError) { 1099 printf("%s: Host interface error\n", 1100 device_xname(sc->sc_dev)); 1101 wantinit = 1; 1102 continue; 1103 } 1104 1105 /* Receive interrupts. */ 1106 if (isr & (IS_RxDMAComplete | IS_RFDListEnd)) { 1107 STGE_EVCNT_INCR(&sc->sc_ev_rxintr); 1108 stge_rxintr(sc); 1109 if (isr & IS_RFDListEnd) { 1110 printf("%s: receive ring overflow\n", 1111 device_xname(sc->sc_dev)); 1112 /* 1113 * XXX Should try to recover from this 1114 * XXX more gracefully. 1115 */ 1116 wantinit = 1; 1117 } 1118 } 1119 1120 /* Transmit interrupts. */ 1121 if (isr & (IS_TxDMAComplete | IS_TxComplete)) { 1122 #ifdef STGE_EVENT_COUNTERS 1123 if (isr & IS_TxDMAComplete) 1124 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr); 1125 #endif 1126 stge_txintr(sc); 1127 } 1128 1129 /* Statistics overflow. */ 1130 if (isr & IS_UpdateStats) 1131 stge_stats_update(sc); 1132 1133 /* Transmission errors. */ 1134 if (isr & IS_TxComplete) { 1135 STGE_EVCNT_INCR(&sc->sc_ev_txindintr); 1136 for (;;) { 1137 txstat = CSR_READ_4(sc, STGE_TxStatus); 1138 if ((txstat & TS_TxComplete) == 0) 1139 break; 1140 if (txstat & TS_TxUnderrun) { 1141 sc->sc_txthresh++; 1142 if (sc->sc_txthresh > 0x0fff) 1143 sc->sc_txthresh = 0x0fff; 1144 printf("%s: transmit underrun, new " 1145 "threshold: %d bytes\n", 1146 device_xname(sc->sc_dev), 1147 sc->sc_txthresh << 5); 1148 } 1149 if (txstat & TS_MaxCollisions) 1150 printf("%s: excessive collisions\n", 1151 device_xname(sc->sc_dev)); 1152 } 1153 wantinit = 1; 1154 } 1155 1156 } 1157 1158 if (wantinit) 1159 stge_init(ifp); 1160 1161 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1162 1163 /* Try to get more packets going. */ 1164 if_schedule_deferred_start(ifp); 1165 1166 return (1); 1167 } 1168 1169 /* 1170 * stge_txintr: 1171 * 1172 * Helper; handle transmit interrupts. 1173 */ 1174 static void 1175 stge_txintr(struct stge_softc *sc) 1176 { 1177 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1178 struct stge_descsoft *ds; 1179 uint64_t control; 1180 int i; 1181 1182 /* 1183 * Go through our Tx list and free mbufs for those 1184 * frames which have been transmitted. 1185 */ 1186 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 1187 i = STGE_NEXTTX(i), sc->sc_txpending--) { 1188 ds = &sc->sc_txsoft[i]; 1189 1190 STGE_CDTXSYNC(sc, i, 1191 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1192 1193 control = le64toh(sc->sc_txdescs[i].tfd_control); 1194 if ((control & TFD_TFDDone) == 0) 1195 break; 1196 1197 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 1198 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1199 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1200 m_freem(ds->ds_mbuf); 1201 ds->ds_mbuf = NULL; 1202 } 1203 1204 /* Update the dirty transmit buffer pointer. */ 1205 sc->sc_txdirty = i; 1206 1207 /* 1208 * If there are no more pending transmissions, cancel the watchdog 1209 * timer. 1210 */ 1211 if (sc->sc_txpending == 0) 1212 ifp->if_timer = 0; 1213 } 1214 1215 /* 1216 * stge_rxintr: 1217 * 1218 * Helper; handle receive interrupts. 1219 */ 1220 static void 1221 stge_rxintr(struct stge_softc *sc) 1222 { 1223 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1224 struct stge_descsoft *ds; 1225 struct mbuf *m, *tailm; 1226 uint64_t status; 1227 int i, len; 1228 1229 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) { 1230 ds = &sc->sc_rxsoft[i]; 1231 1232 STGE_CDRXSYNC(sc, i, 1233 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1234 1235 status = le64toh(sc->sc_rxdescs[i].rfd_status); 1236 1237 if ((status & RFD_RFDDone) == 0) 1238 break; 1239 1240 if (__predict_false(sc->sc_rxdiscard)) { 1241 STGE_INIT_RXDESC(sc, i); 1242 if (status & RFD_FrameEnd) { 1243 /* Reset our state. */ 1244 sc->sc_rxdiscard = 0; 1245 } 1246 continue; 1247 } 1248 1249 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1250 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1251 1252 m = ds->ds_mbuf; 1253 1254 /* 1255 * Add a new receive buffer to the ring. 1256 */ 1257 if (stge_add_rxbuf(sc, i) != 0) { 1258 /* 1259 * Failed, throw away what we've done so 1260 * far, and discard the rest of the packet. 1261 */ 1262 if_statinc(ifp, if_ierrors); 1263 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1264 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1265 STGE_INIT_RXDESC(sc, i); 1266 if ((status & RFD_FrameEnd) == 0) 1267 sc->sc_rxdiscard = 1; 1268 m_freem(sc->sc_rxhead); 1269 STGE_RXCHAIN_RESET(sc); 1270 continue; 1271 } 1272 1273 #ifdef DIAGNOSTIC 1274 if (status & RFD_FrameStart) { 1275 KASSERT(sc->sc_rxhead == NULL); 1276 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead); 1277 } 1278 #endif 1279 1280 STGE_RXCHAIN_LINK(sc, m); 1281 1282 /* 1283 * If this is not the end of the packet, keep 1284 * looking. 1285 */ 1286 if ((status & RFD_FrameEnd) == 0) { 1287 sc->sc_rxlen += m->m_len; 1288 continue; 1289 } 1290 1291 /* 1292 * Okay, we have the entire packet now... 1293 */ 1294 *sc->sc_rxtailp = NULL; 1295 m = sc->sc_rxhead; 1296 tailm = sc->sc_rxtail; 1297 1298 STGE_RXCHAIN_RESET(sc); 1299 1300 /* 1301 * If the packet had an error, drop it. Note we 1302 * count the error later in the periodic stats update. 1303 */ 1304 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame | 1305 RFD_RxAlignmentError | RFD_RxFCSError | 1306 RFD_RxLengthError)) { 1307 m_freem(m); 1308 continue; 1309 } 1310 1311 /* 1312 * No errors. 1313 * 1314 * Note we have configured the chip to not include 1315 * the CRC at the end of the packet. 1316 */ 1317 len = RFD_RxDMAFrameLen(status); 1318 tailm->m_len = len - sc->sc_rxlen; 1319 1320 /* 1321 * If the packet is small enough to fit in a 1322 * single header mbuf, allocate one and copy 1323 * the data into it. This greatly reduces 1324 * memory consumption when we receive lots 1325 * of small packets. 1326 */ 1327 if (stge_copy_small != 0 && len <= (MHLEN - 2)) { 1328 struct mbuf *nm; 1329 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1330 if (nm == NULL) { 1331 if_statinc(ifp, if_ierrors); 1332 m_freem(m); 1333 continue; 1334 } 1335 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1336 nm->m_data += 2; 1337 nm->m_pkthdr.len = nm->m_len = len; 1338 m_copydata(m, 0, len, mtod(nm, void *)); 1339 m_freem(m); 1340 m = nm; 1341 } 1342 1343 /* 1344 * Set the incoming checksum information for the packet. 1345 */ 1346 if (status & RFD_IPDetected) { 1347 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum); 1348 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1349 if (status & RFD_IPError) 1350 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1351 if (status & RFD_TCPDetected) { 1352 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1353 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1354 if (status & RFD_TCPError) 1355 m->m_pkthdr.csum_flags |= 1356 M_CSUM_TCP_UDP_BAD; 1357 } else if (status & RFD_UDPDetected) { 1358 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1359 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1360 if (status & RFD_UDPError) 1361 m->m_pkthdr.csum_flags |= 1362 M_CSUM_TCP_UDP_BAD; 1363 } 1364 } 1365 1366 m_set_rcvif(m, ifp); 1367 m->m_pkthdr.len = len; 1368 1369 /* 1370 * Pass this up to any BPF listeners, but only 1371 * pass if up the stack if it's for us. 1372 */ 1373 #ifdef STGE_VLAN_UNTAG 1374 /* 1375 * Check for VLAN tagged packets 1376 */ 1377 if (status & RFD_VLANDetected) 1378 vlan_set_tag(m, RFD_TCI(status)); 1379 1380 #endif 1381 #if 0 1382 if (status & RFD_VLANDetected) { 1383 struct ether_header *eh; 1384 uint16_t etype; 1385 1386 eh = mtod(m, struct ether_header *); 1387 etype = ntohs(eh->ether_type); 1388 printf("%s: VLANtag detected (TCI %d) etype %x\n", 1389 ifp->if_xname, (uint16_t) RFD_TCI(status), 1390 etype); 1391 } 1392 #endif 1393 /* Pass it on. */ 1394 if_percpuq_enqueue(ifp->if_percpuq, m); 1395 } 1396 1397 /* Update the receive pointer. */ 1398 sc->sc_rxptr = i; 1399 } 1400 1401 /* 1402 * stge_tick: 1403 * 1404 * One second timer, used to tick the MII. 1405 */ 1406 static void 1407 stge_tick(void *arg) 1408 { 1409 struct stge_softc *sc = arg; 1410 int s; 1411 1412 s = splnet(); 1413 mii_tick(&sc->sc_mii); 1414 stge_stats_update(sc); 1415 splx(s); 1416 1417 callout_schedule(&sc->sc_tick_ch, hz); 1418 } 1419 1420 /* 1421 * stge_stats_update: 1422 * 1423 * Read the TC9021 statistics counters. 1424 */ 1425 static void 1426 stge_stats_update(struct stge_softc *sc) 1427 { 1428 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1429 1430 (void) CSR_READ_4(sc, STGE_OctetRcvOk); 1431 1432 (void) CSR_READ_4(sc, STGE_FramesRcvdOk); 1433 1434 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1435 1436 if_statadd_ref(ifp, nsr, if_ierrors, 1437 (u_int) CSR_READ_2(sc, STGE_FramesLostRxErrors)); 1438 1439 (void) CSR_READ_4(sc, STGE_OctetXmtdOk); 1440 1441 if_statadd_ref(ifp, nsr, if_opackets, 1442 CSR_READ_4(sc, STGE_FramesXmtdOk)); 1443 1444 if_statadd_ref(ifp, nsr, if_collisions, 1445 CSR_READ_4(sc, STGE_LateCollisions) + 1446 CSR_READ_4(sc, STGE_MultiColFrames) + 1447 CSR_READ_4(sc, STGE_SingleColFrames)); 1448 1449 if_statadd_ref(ifp, nsr, if_oerrors, 1450 (u_int) CSR_READ_2(sc, STGE_FramesAbortXSColls) + 1451 (u_int) CSR_READ_2(sc, STGE_FramesWEXDeferal)); 1452 1453 IF_STAT_PUTREF(ifp); 1454 } 1455 1456 /* 1457 * stge_reset: 1458 * 1459 * Perform a soft reset on the TC9021. 1460 */ 1461 static void 1462 stge_reset(struct stge_softc *sc) 1463 { 1464 uint32_t ac; 1465 int i; 1466 1467 ac = CSR_READ_4(sc, STGE_AsicCtrl); 1468 1469 /* 1470 * Only assert RstOut if we're fiber. We need GMII clocks 1471 * to be present in order for the reset to complete on fiber 1472 * cards. 1473 */ 1474 CSR_WRITE_4(sc, STGE_AsicCtrl, 1475 ac | AC_GlobalReset | AC_RxReset | AC_TxReset | 1476 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit | 1477 (sc->sc_usefiber ? AC_RstOut : 0)); 1478 1479 delay(50000); 1480 1481 for (i = 0; i < STGE_TIMEOUT; i++) { 1482 delay(5000); 1483 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) 1484 break; 1485 } 1486 1487 if (i == STGE_TIMEOUT) 1488 printf("%s: reset failed to complete\n", 1489 device_xname(sc->sc_dev)); 1490 1491 delay(1000); 1492 } 1493 1494 /* 1495 * stge_init: [ ifnet interface function ] 1496 * 1497 * Initialize the interface. Must be called at splnet(). 1498 */ 1499 static int 1500 stge_init(struct ifnet *ifp) 1501 { 1502 struct stge_softc *sc = ifp->if_softc; 1503 struct stge_descsoft *ds; 1504 int i, error = 0; 1505 1506 /* 1507 * Cancel any pending I/O. 1508 */ 1509 stge_stop(ifp, 0); 1510 1511 /* 1512 * Reset the chip to a known state. 1513 */ 1514 stge_reset(sc); 1515 1516 /* 1517 * Initialize the transmit descriptor ring. 1518 */ 1519 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1520 for (i = 0; i < STGE_NTXDESC; i++) { 1521 sc->sc_txdescs[i].tfd_next = htole64( 1522 STGE_CDTXADDR(sc, STGE_NEXTTX(i))); 1523 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); 1524 } 1525 sc->sc_txpending = 0; 1526 sc->sc_txdirty = 0; 1527 sc->sc_txlast = STGE_NTXDESC - 1; 1528 1529 /* 1530 * Initialize the receive descriptor and receive job 1531 * descriptor rings. 1532 */ 1533 for (i = 0; i < STGE_NRXDESC; i++) { 1534 ds = &sc->sc_rxsoft[i]; 1535 if (ds->ds_mbuf == NULL) { 1536 if ((error = stge_add_rxbuf(sc, i)) != 0) { 1537 printf("%s: unable to allocate or map rx " 1538 "buffer %d, error = %d\n", 1539 device_xname(sc->sc_dev), i, error); 1540 /* 1541 * XXX Should attempt to run with fewer receive 1542 * XXX buffers instead of just failing. 1543 */ 1544 stge_rxdrain(sc); 1545 goto out; 1546 } 1547 } else 1548 STGE_INIT_RXDESC(sc, i); 1549 } 1550 sc->sc_rxptr = 0; 1551 sc->sc_rxdiscard = 0; 1552 STGE_RXCHAIN_RESET(sc); 1553 1554 /* Set the station address. */ 1555 for (i = 0; i < 6; i++) 1556 CSR_WRITE_1(sc, STGE_StationAddress0 + i, 1557 CLLADDR(ifp->if_sadl)[i]); 1558 1559 /* 1560 * Set the statistics masks. Disable all the RMON stats, 1561 * and disable selected stats in the non-RMON stats registers. 1562 */ 1563 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff); 1564 CSR_WRITE_4(sc, STGE_StatisticsMask, 1565 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) | 1566 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) | 1567 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) | 1568 (1U << 21)); 1569 1570 /* Set up the receive filter. */ 1571 stge_set_filter(sc); 1572 1573 /* 1574 * Give the transmit and receive ring to the chip. 1575 */ 1576 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 1577 ((uint64_t)STGE_CDTXADDR(sc, sc->sc_txdirty)) >> 32); 1578 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 1579 STGE_CDTXADDR(sc, sc->sc_txdirty)); 1580 1581 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 1582 ((uint64_t)STGE_CDRXADDR(sc, sc->sc_rxptr)) >> 32); 1583 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 1584 STGE_CDRXADDR(sc, sc->sc_rxptr)); 1585 1586 /* 1587 * Initialize the Tx auto-poll period. It's OK to make this number 1588 * large (255 is the max, but we use 127) -- we explicitly kick the 1589 * transmit engine when there's actually a packet. 1590 */ 1591 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); 1592 1593 /* ..and the Rx auto-poll period. */ 1594 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 64); 1595 1596 /* Initialize the Tx start threshold. */ 1597 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); 1598 1599 /* RX DMA thresholds, from linux */ 1600 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); 1601 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); 1602 1603 /* Rx early threhold, from Linux */ 1604 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); 1605 1606 /* Tx DMA thresholds, from Linux */ 1607 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); 1608 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); 1609 1610 /* 1611 * Initialize the Rx DMA interrupt control register. We 1612 * request an interrupt after every incoming packet, but 1613 * defer it for 32us (64 * 512 ns). When the number of 1614 * interrupts pending reaches 8, we stop deferring the 1615 * interrupt, and signal it immediately. 1616 */ 1617 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl, 1618 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512)); 1619 1620 /* 1621 * Initialize the interrupt mask. 1622 */ 1623 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats | 1624 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd; 1625 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff); 1626 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); 1627 1628 /* 1629 * Configure the DMA engine. 1630 * XXX Should auto-tune TxBurstLimit. 1631 */ 1632 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | 1633 DMAC_TxBurstLimit(3)); 1634 1635 /* 1636 * Send a PAUSE frame when we reach 29,696 bytes in the Rx 1637 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes 1638 * in the Rx FIFO. 1639 */ 1640 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); 1641 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16); 1642 1643 /* 1644 * Set the maximum frame size. 1645 */ 1646 CSR_WRITE_2(sc, STGE_MaxFrameSize, 1647 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1648 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 1649 ETHER_VLAN_ENCAP_LEN : 0)); 1650 1651 /* 1652 * Initialize MacCtrl -- do it before setting the media, 1653 * as setting the media will actually program the register. 1654 * 1655 * Note: We have to poke the IFS value before poking 1656 * anything else. 1657 */ 1658 sc->sc_MACCtrl = MC_IFSSelect(0); 1659 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 1660 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable; 1661 #ifdef STGE_VLAN_UNTAG 1662 sc->sc_MACCtrl |= MC_AutoVLANuntagging; 1663 #endif 1664 1665 if (sc->sc_rev >= 6) { /* >= B.2 */ 1666 /* Multi-frag frame bug work-around. */ 1667 CSR_WRITE_2(sc, STGE_DebugCtrl, 1668 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200); 1669 1670 /* Tx Poll Now bug work-around. */ 1671 CSR_WRITE_2(sc, STGE_DebugCtrl, 1672 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010); 1673 /* XXX ? from linux */ 1674 CSR_WRITE_2(sc, STGE_DebugCtrl, 1675 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020); 1676 } 1677 1678 /* 1679 * Set the current media. 1680 */ 1681 if ((error = ether_mediachange(ifp)) != 0) 1682 goto out; 1683 1684 /* 1685 * Start the one second MII clock. 1686 */ 1687 callout_schedule(&sc->sc_tick_ch, hz); 1688 1689 /* 1690 * ...all done! 1691 */ 1692 ifp->if_flags |= IFF_RUNNING; 1693 1694 out: 1695 if (error) 1696 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1697 return (error); 1698 } 1699 1700 /* 1701 * stge_drain: 1702 * 1703 * Drain the receive queue. 1704 */ 1705 static void 1706 stge_rxdrain(struct stge_softc *sc) 1707 { 1708 struct stge_descsoft *ds; 1709 int i; 1710 1711 for (i = 0; i < STGE_NRXDESC; i++) { 1712 ds = &sc->sc_rxsoft[i]; 1713 if (ds->ds_mbuf != NULL) { 1714 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1715 ds->ds_mbuf->m_next = NULL; 1716 m_freem(ds->ds_mbuf); 1717 ds->ds_mbuf = NULL; 1718 } 1719 } 1720 } 1721 1722 /* 1723 * stge_stop: [ ifnet interface function ] 1724 * 1725 * Stop transmission on the interface. 1726 */ 1727 static void 1728 stge_stop(struct ifnet *ifp, int disable) 1729 { 1730 struct stge_softc *sc = ifp->if_softc; 1731 struct stge_descsoft *ds; 1732 int i; 1733 1734 /* 1735 * Stop the one second clock. 1736 */ 1737 callout_stop(&sc->sc_tick_ch); 1738 1739 /* Down the MII. */ 1740 mii_down(&sc->sc_mii); 1741 1742 /* 1743 * Disable interrupts. 1744 */ 1745 CSR_WRITE_2(sc, STGE_IntEnable, 0); 1746 1747 /* 1748 * Stop receiver, transmitter, and stats update. 1749 */ 1750 CSR_WRITE_4(sc, STGE_MACCtrl, 1751 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable); 1752 1753 /* 1754 * Stop the transmit and receive DMA. 1755 */ 1756 stge_dma_wait(sc); 1757 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0); 1758 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0); 1759 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0); 1760 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0); 1761 1762 /* 1763 * Release any queued transmit buffers. 1764 */ 1765 for (i = 0; i < STGE_NTXDESC; i++) { 1766 ds = &sc->sc_txsoft[i]; 1767 if (ds->ds_mbuf != NULL) { 1768 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1769 m_freem(ds->ds_mbuf); 1770 ds->ds_mbuf = NULL; 1771 } 1772 } 1773 1774 /* 1775 * Mark the interface down and cancel the watchdog timer. 1776 */ 1777 ifp->if_flags &= ~IFF_RUNNING; 1778 ifp->if_timer = 0; 1779 1780 if (disable) 1781 stge_rxdrain(sc); 1782 } 1783 1784 static int 1785 stge_eeprom_wait(struct stge_softc *sc) 1786 { 1787 int i; 1788 1789 for (i = 0; i < STGE_TIMEOUT; i++) { 1790 delay(1000); 1791 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0) 1792 return (0); 1793 } 1794 return (1); 1795 } 1796 1797 /* 1798 * stge_read_eeprom: 1799 * 1800 * Read data from the serial EEPROM. 1801 */ 1802 static void 1803 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data) 1804 { 1805 1806 if (stge_eeprom_wait(sc)) 1807 printf("%s: EEPROM failed to come ready\n", 1808 device_xname(sc->sc_dev)); 1809 1810 CSR_WRITE_2(sc, STGE_EepromCtrl, 1811 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR)); 1812 if (stge_eeprom_wait(sc)) 1813 printf("%s: EEPROM read timed out\n", 1814 device_xname(sc->sc_dev)); 1815 *data = CSR_READ_2(sc, STGE_EepromData); 1816 } 1817 1818 /* 1819 * stge_add_rxbuf: 1820 * 1821 * Add a receive buffer to the indicated descriptor. 1822 */ 1823 static int 1824 stge_add_rxbuf(struct stge_softc *sc, int idx) 1825 { 1826 struct stge_descsoft *ds = &sc->sc_rxsoft[idx]; 1827 struct mbuf *m; 1828 int error; 1829 1830 MGETHDR(m, M_DONTWAIT, MT_DATA); 1831 if (m == NULL) 1832 return (ENOBUFS); 1833 1834 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1835 MCLGET(m, M_DONTWAIT); 1836 if ((m->m_flags & M_EXT) == 0) { 1837 m_freem(m); 1838 return (ENOBUFS); 1839 } 1840 1841 m->m_data = m->m_ext.ext_buf + 2; 1842 m->m_len = MCLBYTES - 2; 1843 1844 if (ds->ds_mbuf != NULL) 1845 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1846 1847 ds->ds_mbuf = m; 1848 1849 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1850 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 1851 if (error) { 1852 printf("%s: can't load rx DMA map %d, error = %d\n", 1853 device_xname(sc->sc_dev), idx, error); 1854 panic("stge_add_rxbuf"); /* XXX */ 1855 } 1856 1857 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1858 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1859 1860 STGE_INIT_RXDESC(sc, idx); 1861 1862 return (0); 1863 } 1864 1865 /* 1866 * stge_set_filter: 1867 * 1868 * Set up the receive filter. 1869 */ 1870 static void 1871 stge_set_filter(struct stge_softc *sc) 1872 { 1873 struct ethercom *ec = &sc->sc_ethercom; 1874 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1875 struct ether_multi *enm; 1876 struct ether_multistep step; 1877 uint32_t crc; 1878 uint32_t mchash[2]; 1879 1880 sc->sc_ReceiveMode = RM_ReceiveUnicast; 1881 if (ifp->if_flags & IFF_BROADCAST) 1882 sc->sc_ReceiveMode |= RM_ReceiveBroadcast; 1883 1884 /* XXX: ST1023 only works in promiscuous mode */ 1885 if (sc->sc_stge1023) 1886 ifp->if_flags |= IFF_PROMISC; 1887 1888 if (ifp->if_flags & IFF_PROMISC) { 1889 sc->sc_ReceiveMode |= RM_ReceiveAllFrames; 1890 goto allmulti; 1891 } 1892 1893 /* 1894 * Set up the multicast address filter by passing all multicast 1895 * addresses through a CRC generator, and then using the low-order 1896 * 6 bits as an index into the 64 bit multicast hash table. The 1897 * high order bits select the register, while the rest of the bits 1898 * select the bit within the register. 1899 */ 1900 1901 memset(mchash, 0, sizeof(mchash)); 1902 1903 ETHER_LOCK(ec); 1904 ETHER_FIRST_MULTI(step, ec, enm); 1905 if (enm == NULL) { 1906 ETHER_UNLOCK(ec); 1907 goto done; 1908 } 1909 1910 while (enm != NULL) { 1911 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1912 /* 1913 * We must listen to a range of multicast addresses. 1914 * For now, just accept all multicasts, rather than 1915 * trying to set only those filter bits needed to match 1916 * the range. (At this time, the only use of address 1917 * ranges is for IP multicast routing, for which the 1918 * range is big enough to require all bits set.) 1919 */ 1920 ETHER_UNLOCK(ec); 1921 goto allmulti; 1922 } 1923 1924 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1925 1926 /* Just want the 6 least significant bits. */ 1927 crc &= 0x3f; 1928 1929 /* Set the corresponding bit in the hash table. */ 1930 mchash[crc >> 5] |= 1 << (crc & 0x1f); 1931 1932 ETHER_NEXT_MULTI(step, enm); 1933 } 1934 ETHER_UNLOCK(ec); 1935 1936 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash; 1937 1938 ifp->if_flags &= ~IFF_ALLMULTI; 1939 goto done; 1940 1941 allmulti: 1942 ifp->if_flags |= IFF_ALLMULTI; 1943 sc->sc_ReceiveMode |= RM_ReceiveMulticast; 1944 1945 done: 1946 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1947 /* 1948 * Program the multicast hash table. 1949 */ 1950 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]); 1951 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]); 1952 } 1953 1954 CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode); 1955 } 1956 1957 /* 1958 * stge_mii_readreg: [mii interface function] 1959 * 1960 * Read a PHY register on the MII of the TC9021. 1961 */ 1962 static int 1963 stge_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1964 { 1965 1966 return mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg, val); 1967 } 1968 1969 /* 1970 * stge_mii_writereg: [mii interface function] 1971 * 1972 * Write a PHY register on the MII of the TC9021. 1973 */ 1974 static int 1975 stge_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1976 { 1977 1978 return mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, 1979 val); 1980 } 1981 1982 /* 1983 * stge_mii_statchg: [mii interface function] 1984 * 1985 * Callback from MII layer when media changes. 1986 */ 1987 static void 1988 stge_mii_statchg(struct ifnet *ifp) 1989 { 1990 struct stge_softc *sc = ifp->if_softc; 1991 1992 sc->sc_MACCtrl &= ~(MC_DuplexSelect | MC_RxFlowControlEnable | 1993 MC_TxFlowControlEnable); 1994 1995 if (sc->sc_mii.mii_media_active & IFM_FDX) 1996 sc->sc_MACCtrl |= MC_DuplexSelect; 1997 if ((sc->sc_mii.mii_media_active & IFM_ETH_RXPAUSE) != 0) 1998 sc->sc_MACCtrl |= MC_RxFlowControlEnable; 1999 if ((sc->sc_mii.mii_media_active & IFM_ETH_TXPAUSE) != 0) 2000 sc->sc_MACCtrl |= MC_TxFlowControlEnable; 2001 2002 CSR_WRITE_4(sc, STGE_MACCtrl, sc->sc_MACCtrl); 2003 } 2004 2005 /* 2006 * sste_mii_bitbang_read: [mii bit-bang interface function] 2007 * 2008 * Read the MII serial port for the MII bit-bang module. 2009 */ 2010 static uint32_t 2011 stge_mii_bitbang_read(device_t self) 2012 { 2013 struct stge_softc *sc = device_private(self); 2014 2015 return (CSR_READ_1(sc, STGE_PhyCtrl)); 2016 } 2017 2018 /* 2019 * stge_mii_bitbang_write: [mii big-bang interface function] 2020 * 2021 * Write the MII serial port for the MII bit-bang module. 2022 */ 2023 static void 2024 stge_mii_bitbang_write(device_t self, uint32_t val) 2025 { 2026 struct stge_softc *sc = device_private(self); 2027 2028 CSR_WRITE_1(sc, STGE_PhyCtrl, val | sc->sc_PhyCtrl); 2029 } 2030
Indexes created Sat Oct 11 08:10:02 GMT 2025