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    Searched defs:STI (Results 1 - 25 of 200) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.h 23 const ARMSubtarget &STI;
26 explicit ARMFrameLowering(const ARMSubtarget &sti);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiFrameLowering.h 29 const LanaiSubtarget &STI;
36 STI(Subtarget) {}
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFrameLowering.h 24 const MipsSubtarget &STI;
27 explicit MipsFrameLowering(const MipsSubtarget &sti, Align Alignment)
28 : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {
MipsPreLegalizerCombiner.cpp 51 const MipsSubtarget &STI =
56 if (!STI.systemSupportsUnalignedAccess() && isUnaligned)
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVFrameLowering.h 24 explicit RISCVFrameLowering(const RISCVSubtarget &STI)
28 STI(STI) {}
72 const RISCVSubtarget &STI;
RISCVInstrInfo.h 30 explicit RISCVInstrInfo(RISCVSubtarget &STI);
154 const RISCVSubtarget &STI;
RISCVInstructionSelector.cpp 35 const RISCVSubtarget &STI,
44 const RISCVSubtarget &STI;
50 // uses "STI." in the code generated by TableGen. We need to unify the name of
52 const RISCVSubtarget *Subtarget = &STI;
70 const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
72 : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
73 TRI(*STI.getRegisterInfo()), RBI(RBI),
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.h 443 const NVPTXSubtarget &STI);
555 const NVPTXSubtarget &STI; // cache the subtarget here
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEFrameLowering.h 70 const VESubtarget &STI;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMAsmBackend.h 21 // The STI from the target triple the MCAsmBackend was instantiated with
22 // note that MCFragments may have a different local STI that should be
24 const MCSubtargetInfo &STI;
27 ARMAsmBackend(const Target &T, const MCSubtargetInfo &STI,
29 : MCAsmBackend(Endian), STI(STI),
30 isThumbMode(STI.getTargetTriple().isThumb()) {}
36 // FIXME: this should be calculated per fragment as the STI may be
38 bool hasNOP() const { return STI.getFeatureBits()[ARM::HasV6T2Ops]; }
50 const MCSubtargetInfo *STI) const
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kFrameLowering.h 30 const M68kSubtarget &STI;
68 explicit M68kFrameLowering(const M68kSubtarget &sti, Align Alignment);
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
CodeEmitter.h 36 const MCSubtargetInfo &STI;
56 : STI(ST), MAB(AB), MCE(CE), VecOS(Code), Sequence(S),
InstrBuilder.h 39 const MCSubtargetInfo &STI;
62 InstrBuilder(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
Context.h 53 const MCSubtargetInfo &STI;
56 Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
61 const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
DispatchStage.h 54 const MCSubtargetInfo &STI;
InOrderIssueStage.h 33 const MCSubtargetInfo &STI;
83 const MCSubtargetInfo &STI)
84 : SM(SM), STI(STI), PRF(PRF), RM(std::make_unique<ResourceManager>(SM)),
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNRegPressure.cpp 76 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
77 return STI->isSGPRClass(RC) ?
78 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) :
79 STI->hasAGPRs(RC) ?
80 (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) :
81 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCChecker.h 39 MCSubtargetInfo const &STI;
117 MCSubtargetInfo const &STI, MCInst &mcb,
120 MCSubtargetInfo const &STI, bool CopyReportErrors);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVAsmBackend.h 25 const MCSubtargetInfo &STI;
33 RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
35 : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
38 STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName());
39 RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
49 return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax];
76 const MCSubtargetInfo *STI) const override
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86FrameLowering.h 29 X86FrameLowering(const X86Subtarget &STI, MaybeAlign StackAlignOverride);
33 const X86Subtarget &STI;
X86AvoidTrailingCall.cpp 82 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
83 const X86InstrInfo &TII = *STI.getInstrInfo();
84 assert(STI.isTargetWin64() && "pass only runs on Win64");
  /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/
CodeRegionGenerator.h 52 const MCSubtargetInfo &STI;
60 : CodeRegionGenerator(SM), TheTarget(T), Ctx(C), MAI(A), STI(S), MCII(I),
  /src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
InstructionView.h 28 const llvm::MCSubtargetInfo &STI;
38 InstructionView(const llvm::MCSubtargetInfo &STI,
42 : STI(STI), MCIP(Printer), Source(S), MCPU(MCPU),
54 const llvm::MCSubtargetInfo &getSubTargetInfo() const { return STI; }
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUTargetStreamer.h 92 virtual bool EmitCodeEnd(const MCSubtargetInfo &STI) = 0;
95 const MCSubtargetInfo &STI, StringRef KernelName,
108 void initializeTargetID(const MCSubtargetInfo &STI) {
110 TargetID.emplace(STI);
112 void initializeTargetID(const MCSubtargetInfo &STI, StringRef FeatureString) {
113 initializeTargetID(STI);
152 bool EmitCodeEnd(const MCSubtargetInfo &STI) override;
155 const MCSubtargetInfo &STI, StringRef KernelName,
161 const MCSubtargetInfo &STI;
181 AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCExpandPseudos.cpp 77 const ARCSubtarget *STI = &MF.getSubtarget<ARCSubtarget>();
78 TII = STI->getInstrInfo();

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